Experimental Studies of the Reliability of Interconnect Trees
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Experimental Studies of the Reliability of Interconnect Trees S.P. Hau-Riege and C.V. Thompson Department of Materials Science and Engineering, M.I.T., Cambridge, MA ABSTRACT The electromigration resistance of simple straight-line interconnects is usually used to estimate the reliability of complex integrated circuits. This is generally inaccurate, and overly conservative at best. The shapes and connectedness of interconnects is not accounted for in standard reliability assessments. We have identified the interconnect tree as the fundamental reliability unit. An interconnect tree consists of connected conducting line segments lying within a single layer of metallization, and terminating at two or more nodes at which there is a diffusion barrier such as a W-filled via. We performed electromigration experiments on the simplest tree structures, such as âLâ- and âTâ-shaped interconnects, as well as straight lines with an additional via in the middle of the line, passing currents of different magnitudes and directions through the limbs of the trees. We found that metal limbs ending in other limbs can act as reservoirs for electromigrating metal atoms. Passive reservoirs, which are limbs that do not carry electrical current, are generally beneficial for reliability, whereas limbs that do carry electrical current, called active reservoirs, can be beneficial or detrimental, depending on the direction and magnitude of the current in the reservoir. However, our experiments show that bends in interconnects do not affect their reliability significantly. We also found that the reliability of an interconnect tree can be conservatively estimated by considering void-growth and voidnucleation-limited failures at the most heavily stressed junction in the tree, which can be found by analyzing the geometry and current configuration. Our experimentally verified model for tree reliability can be used with layout tools for reliability-driven computer-aided design (RCAD), through ranking of the reliabilities of trees in order to identify areas at risk from electromigration damage. INTRODUCTION Electromigration-induced failure continues to be an important reliability issue for integrated circuits. Electromigration is electronic-current-induced atomic diffusion due to momentum transfer from flowing electrons to host atoms [1-2]. As device dimensions shrink with the introduction of each new generation of technology, the cross sectional area of interconnects becomes smaller, and interconnects carry ever-higher current densities. Current design rules and design practices developed to prevent electromigration-induced failure tend to be overly conservative [3]. To optimize performance for a given technology, while maintaining a high overall reliability, it is necessary to develop a design practice that more accurately, and less conservatively, accounts for the effects of circuit layout on the risk of electromigration-induced failure. To date, modeling, simulation, and experimental analyses of interconnect reliability have primarily focussed on the
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