CMP Challenges for Advanced Technology Nodes
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CMP Challenges for Advanced Technology Nodes John H Zhang1*, Haigou Huang2, Andrew M. Greene3, Ruilong Xie1, Soon-Cheon Seo3, Pietro Montanini3, Wei-Tsu Tseng2, Stan Tsai1, Matthew Malley3, Qiang Fang2, Raghuveer Patlolla3, Dinesh Koli2, Dechao Guo3, Donald F. Canaperi3 , Charan Surisetty3, Jean E Wynne3, Walter Kleemeier1 and Cathy Labelle1 1
GLOBALFOUNDRIES, Albany Nanotechnology Center, 257 Fuller Road, Albany, NY 12203 GLOBALFOUNDRIES, 400 Stone break road extension, Malta, NY 12020 3 IBM Research, Albany Nanotechnology Center, 257 Fuller Road, Albany, NY 12203 *Email: [email protected], [email protected] 2
ABSTRACT The CMP challenges for advanced technology nodes are discussed. Global and local uniformity challenges and their cumulative effects are presented. Uniformity improvements for advanced node integration were achieved through slurry, pad and platen optimization, innovative integration schemes, the reduction of incoming variation and the reduction of cumulative effects. We discuss reduction of typical CMP defect types. Defects resulting from simple mechanisms (foreign material, polish residues) and those resulting from chemical and physical interactions (corrosion, chemical attack, scratches, physical migration) and strategies for control are studied. Defectivity reduction measures include new post-CMP clean chemicals, new slurries and pads and reduction of incoming defectivity. Finally we discuss an observed tradeoff between good defectivity and good uniformity. INTRODUCTION As gate size and interconnect dimensions continue to shrink with each successive new technology node, it is necessary to further improve CMP uniformity while suppressing defectivity to lower target levels for yield improvement at all levels.[1] There are several specific challenges to uniformity. When combined with advanced integration schemes that include thinner hard mask and barrier metal layers, current slurries may not be adequate. Reduction in hard mask thickness reduces the planarization requirement, but increases polish rate sensitivity to pattern density, which can lead to CMP dishing. CMP processes must minimize dishing and hard mask loss yet also be able to remove material from low-lying areas associated with prior level topography. Pattern density variation effects incoming to CMP can further aggravate the challenge for local uniformity control post CMP. Pre CMP process steps such as reactive ion etch can introduce variation in the trench dimension itself and this microloading can in turn exhibit across-wafer variation. These challenges drive the need to develop a CMP process with high planarization efficiency. Defectivity control is also critical to assure good production yield and product reliability. Post CMP cleaning and surface treatment are key steps to control defects [2, 3]. Finally the selection of an appropriate polishing pad is also a critical factor to ensure that the CMP process meets its performance requirements. [4,5]
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