Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO 2 Based
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ORIGINAL PAPER
Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET Suparna Panchanan 1,2 & Reshmi Maity 1 & S. Baishya 3 & N. P. Maity 1 Received: 24 March 2020 / Accepted: 14 July 2020 # Springer Nature B.V. 2020
Abstract In this study, an analytical model for surface potential and threshold voltage for undoped (or lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated using transistor computer aided design (TCAD) simulation. The threshold voltage with channel length 50 nm was compared with the published experimental results achieved from tri-gate FinFET. Separate solutions of 2D Poisson’s equation were obtained for both symmetric and asymmetric double gate FinFET and combined using the perimeter-weighted sum approach to achieve the surface potential for TG-FinFET. The inversion charge model was used to find the threshold voltage of the above mentioned device. The results of the model were obtained for different channel lengths, fin widths and fin heights on the silicon substrate. A comparative study of hafnium dioxide (HfO2) and silicon dioxide (SiO2) for the same oxide thickness was delineated to depict the influence of the high dielectric material on the model of FinFET. As anticipated, the oxide thickness of HfO2 is greater than SiO2 to maintain the same surface potential. The result of the analytical model was well agreed with the TCAD simulation outcome. Hence, it can be considered as a promising model in device technology. Keywords FinFET . Surface potential . Threshold voltage . TCAD . High-k
1 Introduction In this electronic era, the advancement of integrated circuit (IC) technology controls the advancement of nearly every other technology. The better performance such as size, cost and energy consumption is the driving force of the evaluation of IC technology. Therefore, the increasing demand for high packing density, low power consumption and high performance recommends device scaling which was effectively carried out since 1990s [1]. Silicon substrate was replaced with Silicon-On-Insulator (SOI) to reduce the size, parasitic
* N. P. Maity [email protected] 1
Department of Electronics and Communication Engineering, Mizoram University (A Central University), Aizawl 796 004, India
2
Department of Electronics and Communication Engineering, Regent Education and Research Foundation, Kolkata 700 121, India
3
Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam 788 010, India
capacitance and series resistance. It was first used by IBM in 2000. So, the use of SOI is an important footstep in IC technology. Over the last two decades, lots of research works have been executed to customize the scaling of contacted gate pitch and physical gate length to get the high-performance transistor [2]. The reductions of physical parameters such as channel lengths, widths, depths, etc. are not sufficient to obtain a high-performance small-scale d
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