Modeling the Impact of Packaging Stress on Device Performance
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Modeling the Impact of Packaging Stress on Device Performance Xiaopeng Xu and Victor Moroz TCAD R&D, Synopsys, Inc. 700 E. Middlefield Rd, Mountain View, CA 94043, USA ABSTRACT In this study the stress evolution for the entire transistor fabrication process is simulated and the packaging stress is modeled as the external pressure/normal stress acting on the boundaries of the transistor unit cell. The impact on device performance from both the fabrication stress and the packaging stress is investigated using a classical piezo-resistance mobility model. The effect of the packaging stress on device mobility can be either beneficial or detrimental depending on whether the stress is tensile or compressive, on stress pattern, its magnitude, and the transistor type. The results suggest that utilizing both the fabrication stress and the packaging stress for stress engineering can lead to additional device performance enhancements. INTRODUCTION Current silicon technology utilizes mechanical stress engineering to tailor the band-gap and carrier mobility for performance enhancements. The device performance can be significantly improved by the appropriately applied channel stresses [1, 2]. The intentional stresses are introduced into the device channel by means of SiGe source and drain (S/D), strained cap layer, metal gate, shallow trench insulation (STI), etc, during the transistor fabrication process. To fully benefit from channel stress engineering, it is essential to maintain the intentional stresses in the channel. However, unintentional stresses are also generated during the transistor fabrication and packaging steps. While unintentional stresses from fabrication steps such as deposition, etching, thermal ramp, oxidation, and silicidation have received most attention since they are often coupled with the intentional stresses, the impact of residual stresses on device performance from the packaging steps have not been considered in the previous studies. In this study, the impact of residual stresses from chip packaging steps on device electrical performance is investigated using our Technology Computer Aid Design (TCAD) simulation tools. The packaging stresses can be introduced during packaging steps such as wire bonding, solder bumping, chip adhesion to the substrate, glob top covering, etc, and the measured packaging stress can be as large as hundreds of mega-Pascals [3]. In our simulations, the residual stresses are treated as external stresses acting on individual transistor cells. The final simulated channel stresses are the results from multiple contributions including intentional and unintentional sources. Electrical properties of the transistors such as the carrier mobility are then studied with or without considering the packaging stress. The numerical study shows that the residual packaging stress can be either beneficial or detrimental to the device performance depending on the stress pattern, the magnitude, and the transistor type. While the current stress engineering techniques focus on the device fab
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