Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects
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0914-F03-03
Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects Xiaopeng Xu, Dipu Pramanik, and Greg Rollins TCAD DFM Solutions, Synopsys, Inc., 700 E. Middlefield Rd, Mountain View, CA, 94043
ABSTRACT The layout dependence of process stress in Cu/low k interconnects are examined using various stress sources and layout patterns. The anisotropic grain growth stress model is compared with the conventional isotropic intrinsic stress model and the latter is found to underestimate stress concentrations in the dielectric regions near metal line ends. Both the grain growth stress in copper and the thermal mismatch stress in copper and low k dielectrics are considered in the layout dependence study. The results demonstrate that accurate stress evaluation in interconnect structures has to employ geometrical models that include layout variations. Capabilities are developed to extract these geometrical models directly from layout analysis. INTRODUCTION It is well known that high stresses in local regions of an interconnect structure can result in yield or field failures ranging from dielectric cracking, metal voiding, to interface de-bonding and layer de-laminations. The stress related failures have become even more significant with the adoption of low k dielectrics materials, which have very low mechanical strength and large thermal expansion. Recent measurements reveal that the margin between average film stresses and dielectric material strengths has continuously been reduced [1,2]. So it is very important to consider the layout variation impact on process stress modulation at the early stages of layout and process design. There are two main stress sources in metal/dielectric interconnects, the thermal mechanical stress and the intrinsic stress. The thermal mechanical stress originates from thermal expansion mismatches between various materials in an interconnect structure while the intrinsic stress is generated as a consequence of the material formation process. The actual stress profile in an interconnect structure results from the re-distribution of these stress sources satisfying the stress equilibrium conditions under local geometrical constraints. The magnitude of the stress distribution depends strongly on the local geometries that are defined by the mask layout patterns. The ubiquitous layout variations lead to very non-uniform stress distributions in the interconnect structures. However, the local layout related geometry variations have not been considered in the conventional modeling of process stress evolution. In the conventional unit cell approach for stress modeling in interconnects, the geometrical model typically contains only one damascene structure consisting of a bottom dielectric layer, an M1-V1-M2 unit, and a top dielectric layer. Although some geometric effects such as line width can be studied, it is difficult to include layout variation effects using this single metal-via-metal chain structure. In this study, the geometrical model is expanded to include layout variat
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