Integration Challenges for Advanced Salicide Processes and their Impact on CMOS Device Performance
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Integration Challenges For Advanced Salicide Processes And Their Impact On CMOS Device Performance K. WIECZOREK1, M. HORSTMANN1, H.-J. ENGELMANN1, K. DITTMAR1, W. BLUM1, A. SULTAN2, P. BESSER2 , A. FRENKEL2 1 2
AMD Saxony Manufacturing GmbH, Postfach 110110, D-01330 Dresden, Germany AMD-Motorola Logic Alliance, 3501 Ed Bluestein Blvd., Austin, TX 78721
ABSTRACT CoSi2 has emerged as the silicide of choice for 0.18µm CMOS technologies and below. Robustness and scaling-performance of an integrated CoSi2-module, however, is shown to critically depend upon careful optimization of each individual process-step. The impact of surface-preparation, capping layer, initial Co-thickness and thermal processing will be discussed. The scalability of an optimized process meeting all major requirements for application to ULSI devices is demonstrated for gate-length down to 60nm. INTRODUCTION With minimum gate features for advanced CMOS-technologies approaching the sub-100nm range, reliable low-resistive silicide formation is a continuos manufacturability-challenge. For it’s compatibly with major integration requirements [1], TiSi2 has been the most widely applied material to ensure both low gate-delays and low-ohmic contacts to source and drain of CMOS devices. Decreasing gate geometries, however, stressed the downsides of the nucleation-andgrowth dominated C49 to C54 conversion required for low-resistive TiSi2-formation. Though high-dose preamorphization ion-implantation (PAI) or metal doping of the initial Ti-layer have been shown to significantly extend the scaling-performance of TiSi2 [2], CoSi2 has emerged as a
Fig. 1: Silicided gate sheet-resistance vs. gate-length comparing CoSi2 formed from 9nm to 13nm initial Co-thickness against a high-energy preamorphization (PAI) TiSi2-process for a) n+-doped polysilicon and b) p+-doped polysilicon.
C5.1.1
replacement with the introduction of 0.18µm process technologies into volume manufacturing. While CoSi2 features an excellent narrow line sheet-resistance scalability down to well below 100nm on both n+- and p+-doped polysilicon even for aggressively scaled Co-layers (Fig. 1), it’s compliance with ultra-shallow junctions depends strongly on the details of the formation sequence [3]. Combining low gate- and source/drain-sheet-resistance requirements with the necessity to maintain ultra-shallow junction integrity requires subtle balancing of all processes within an integrated CoSi2-module. SURFACE PREPARATION Since Ti has the capability of even reducing thin residual SiO2 surface layers during the 1st RTA process due to it’s high chemical reactivity, surface-cleaning has traditionally not been a major concern for reliable TiSi2 formation. Even low-level surface contamination, however, has a profound effect on the control of the electrical and morphological characteristics of integrated CoSi2-layers. Fig. 2 shows the impact of surface cleaning conditions on diode-leakage distributions. All samples were cleaned using a conventional RCA-chemistry and a subsequent
Fig. 2: Diode leakage
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