Molecular Beam Epitaxy Growth of High Mobility Compound Semiconductor Devices for Integration with Si CMOS
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1194-A09-01
Molecular Beam Epitaxy Growth of High Mobility Compound Semiconductor Devices for Integration with Si CMOS D. Lubyshev,1 J. M. Fastenau,1 Y. Wu,1 A. Synder,1 W. K. Liu1*, M. T. Bulsara,2 E. A. Fitzgerald, 1 M. Urteaga, 3 W. Ha, 3 J. Bergman, 3 M. J. Choe, 3 B. Brar,3 W. E. Hoke, 4 J. R. LaRoche, 4 A. Torabi,4 T. E. Kazior,4 D. Smith,5 D. Clark,5 R. F. Thompson,5 C. Drazek,6 N. Daval,6 L. Benaissa7 and E. Augendre7 1 IQE Inc., 119 Technology Drive, Bethlehem, PA 18015, USA; *[email protected] 2 Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, USA 3 Teledyne Scientific Company, Thousand Oaks, California, USA 4 Raytheon Integrated Defense Systems, Andover, Massachusetts, USA 5 Raytheon Systems Ltd., Glenrothes, Fife, Scotland, UK 6 SOITEC, Parc Technologique des Fontaines, Bernin, Crolles Cedex, France 7 CEA-LETI, MINATEC, Grenoble, France ABSTRACT We report on a direct epitaxial growth approach for the heterogeneous integration of high speed III-V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBTs) structures were successfully grown on patterned Si-on-LatticeEngineered-Substrate (SOLES) substrates using molecular beam epitaxy. DC and RF performance similar to those grown on lattice-matched InP were achieved in growth windows as small as 15×15 µm2. This truly planar approach allows tight device placement with InP-HBTs to Si CMOS transistors separation as small as 2.5 µm, and the use of standard wafer level multilayer interconnects. A high speed, low power dissipation differential amplifier was designed and fabricated, demonstrating the feasibility of using this approach for high performance mixed signal circuits such as ADCs and DACs. INTRODUCTION Mainstream silicon (Si) CMOS technology is finally running headlong into limitations of pure Si-based material and process. To extend Moore’s law, key players in the Si industry are increasingly interested in alternative materials and technologies to enhance channel transport properties and reduce power dissipation in future generation transistor circuitry. One very promising path for such improvement is the use of compound III-V semiconductors, as the heterogeneous integration of III-V devices on Si may realize high performance integrated circuits (ICs) for analog and digital applications. A successful integration scheme will provide circuit designers with the technological flexibility to achieve myriad applications without compromising the yield and scalability of CMOS or the speed and breakdown of the III-V devices. Despite significant efforts in the last 20 years from major research groups and semiconductor manufacturers, the potential of such heterogeneous integration has not been fully realized due to the relatively poor material quality of III-V films grown on Si, and due to the limited scalability and integration complexity of III-V technology compared to advanced Si CMOS. Currently, there is ongoing interest in monolithic integration of III-V
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