SiGe channels for higher mobility CMOS devices
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1194-A04-04
SiGe channels for higher mobility CMOS devices Andreas Naumann1,2, Torben Kelwing1,2, Martin Trentzsch2, Stephan Kronholz2, Thorsten Kammler2, Stefan Flachowsky2,4, Tom Herrmann4, Peter Kücher1 and Johann W. Bartha3 1
Fraunhofer Center for Nanoelectronic Technologies, Königsbrücker Str. 180, 01099 Dresden, Germany 2 GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstraße 101, 01109 Dresden, Germany 3 IHM, TU Dresden, Nöthnitzer Str. 64, 01187 Dresden, Germany 4 ZAFT e.V. at HTW Dresden, Friedrich List Platz 1, 01069 Dresden, Germany ABSTRACT Silicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of nand p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method. INTRODUCTION Mobility engineering of transistor channel has become essential in the latest CMOS technologies. Nowadays, strain techniques such as embedded silicon germanium (eSiGe) in the source and drain region (S/D) or compressive and/or tensile etch stop layer on top of the transistor structure are state of the art. For future technology generations the substitution of silicon (Si) by a material with intrinsically higher charge carrier mobility is considered to be necessary for shrinking transistor dimensions further [1,2]. In this paper the benefit of SiGe surface channels with low enough Ge concentrations to be compatible with conventional CMOS manufacturing technologies is discussed.
EXPERIMENT For the fabrication of MOS transistors, a CMOS SOI Technology was used. This technology includes high-k metal gate with sub 50nm gate length, dual stress liner (DSL) and eSiGe [3,4]. For this work only a SiGe epitaxy step was added prior to the gate stack deposition, while all other process steps of the CMOS fabrication remained unchanged. A standard wet cleaning procedure prior to epitaxy (SC1, SC2 and diluted HF), followed by a hydrogen prebake inside the deposition chamber was used. By low pressure chemical vapor deposition
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