Monolithic Integration of Electronics and Sub-wavelength Metal Optics in Deep Submicron CMOS Technology
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D1.5.1
Monolithic Integration of Electronics and Sub-wavelength Metal Optics in Deep Submicron CMOS Technology
Peter B. Catrysse Edward L. Ginzton Laboratory, Department of Electrical Engineering, Stanford University, Stanford, CA 94305-4088, U.S.A.
ABSTRACT The structures that can be implemented and the materials that are used in complementary metal-oxide semiconductor (CMOS) integrated circuit (IC) technology are optimized for electronic performance. However, they are also suitable for manipulating and detecting optical signals. In this paper, we show that while CMOS scaling trends are motivated by improved electronic performance, they are also creating new opportunities for controlling and detecting optical signals at the nanometer scale. For example, in 90-nm CMOS technology the minimum feature size of metal interconnects reaches below 100 nm. This enables the design of nano-slits and nano-apertures that allow control of optical signals at sub-wavelength dimensions. The ability to engineer materials at the nanoscale even holds the promise of creating meta-materials with optical properties, which are unlike those found in the world around us. As an early example of the monolithic integration of electronics and sub-wavelength metal optics, we focus on integrated color pixels (ICPs), a novel color architecture for CMOS image sensors. Following the trend of increased integration in the field of CMOS image sensors, we recently integrated color-filtering capabilities inside image sensor pixels. Specifically, we demonstrated wavelength selectivity of sub-wavelength patterned metal layers in a 180-nm CMOS technology. To fulfill the promise of monolithic photonic integration and to design useful nanophotonic components, such as those employed in ICPs, we argue that analytical models capturing the underlying physical mechanisms of light-matter interaction are of utmost importance.
INTRODUCTION Device dimensions in 21st-century complementary metal oxide semiconductor (CMOS) technology are reaching well into the nanometer regime [1]. While scaling enables increased clock speeds for central processing units (CPUs) and chip densities for random access memories (RAM), it also opens up opportunities for photonic device fabrication. In fact, integrated optics and photonics devices are already being implemented using processing techniques that are directly leveraged from semiconductor technology [2]. In this section, we briefly introduce CMOS technology and we evaluate some of its characteristics and its suitability from a photonics point of view. CMOS technology is a complete process flow sequence, in which several technologies are combined to produce very large scale integrated (VLSI) circuit chips. Two important technologies in this flow are the front-end and the back-end technology.
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Back-end Technology Metal-Metal Capacitor
Metal Interconnects
(a)
(b)
(a) Plasmonic Waveguides
Junction Diode
Subwavelength Metal Filter
MOS Transistor source
(b)
(c)
gate
drain
(c)
(d) n+
(d)
p-substrate
Photodiode
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