Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion
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Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion Igor Polishchuk, Pushkar Ranade, Tsu-Jae King and Chenming Hu Department of Electrical Engineering and Computer Sciences University of California at Berkeley, Berkeley, CA 94720
ABSTRACT In this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET’s. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.
INTRODUCTION Reduction of the capacitance-equivalent thickness (CET) of gate dielectric remains a major challenge for scaling CMOS technology beyond the 100-nm node. The use of high-K dielectrics will allow a significant reduction of the equivalent oxide thickness of the gate dielectric itself. However, there are additional factors, such as polysilicon-depletion effect (PDE) contributing to the total CET of gate dielectrics [1]. As the thickness of the dielectric itself is further reduced the contribution from PDE becomes even more important. Replacing polysilicon gate with a metal gate will essentially eliminate gate depletion and consequently reduce the CET by a few angstroms. In addition, polysilicon gates are thermodynamically unstable on many high-K materials, such as Ta2O5 [2] and ZrO2 [3] for example. Many metals at the same time are expected to be stable on advanced gate dielectrics. A major advantage of the polysilicon gates is that by doping polysilicon with either acceptor or donor atoms one can change the work function of the gate electrode and thus achieve the desirable threshold voltages for both p-MOSFET and n-MOSFET. Since modifying the work function of a metal is much harder one will likely have to use two separate metals (one with a high work function of around 5 eV and the other with a low work function of around 4 eV) in order to achieve the desirable threshold voltages for both p-MOSFET and n-MOSFET bulk CMOS devices. A straightforward way to implement dual work function metal gate CMOS [4] is as follows: After blanket deposition, the first metal is removed from either the p-MOS or nMOS side, and then a second metal with a different work function is deposited. Unfortunately, this entails exposing the gate dielectric to the etchant, leading to undesirable dielectric thinning and potential dielectric reliability problems. We propose an alternative approach in which dual work function gates can be fabricated without exposing the gate dielectric to the etchant. First deposit a thin layer of one of the metals over the entire wafer. For sake of discussion, let us assume this first metal is the one with the low work function. Then deposit the second (high work function) metal
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