Nanoelectronics, Circuits and Nanoprocessors
As electronic device features have been pushed into the deep sub-100-nm regime, conventional scaling strategies in the semiconductor industry have faced technological and economic challenges. Electronics obtained through the bottom-up approach of molecula
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Nanoelectronics, Circuits and Nanoprocessors
Abstract As electronic device features have been pushed into the deep sub-100-nm regime, conventional scaling strategies in the semiconductor industry have faced technological and economic challenges. Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies as well as new architectures not readily accessible or even possible within the context of the top-down driven industry and manufacturing infrastructure. This chapter presents a summary of recent advances in basic nanoelectronics devices, simple circuits and nanoprocessors assembled by semiconductor NWs.
5.1
Introduction and Historical Perspective
In 1965, Gordon Moore, the cofounder of the Intel Corporation, predicted that the number of on-chip transistors doubles approximately every two years, known as the “Moore’s law” [1]. Over the past four decades, sustained advances in integrated circuit technologies for memory and processors have followed this prediction, thereby leading to computers with ever more powerful processing capabilities, ever increasing nonvolatile memory capacity and a host of consumer electronics. But as device features continue to be pushed deep in the sub-100-nm regime, continuation of the scaling predictions of Moore’s law faces substantial fundamental, technological and economic challenges [2–4]. For example, device size fluctuations may result in a large spread in device characteristics at the nanoscale, affecting key parameters such as the threshold voltage and On/Off currents [3, 4]. In addition, the increasing costs associated with lithography equipment and operating facilities needed for conventional manufacturing might also create a huge economic barrier to continued increases in the capabilities of conventional processor and memory chips [3, 4]. Given these recognized challenges, researchers have intensively explored bottom-up and hybrid bottom-up/top-down paradigms in search of alternative approaches to continued scaling of electronic devices [5–9]. In this regard, one of © Springer International Publishing Switzerland 2016 A. Zhang et al., Nanowires, NanoScience and Technology, DOI 10.1007/978-3-319-41981-7_5
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5 Nanoelectronics, Circuits and Nanoprocessors
the most prominent classes of bottom-up nanostructure materials investigated has been NWs. Semiconductor NWs are especially attractive building blocks for electronic devices because they can be synthesized with precisely controlled size, composition, doping and heterostructures [5, 9–12]. In addition and as described in the previous chapter, NWs can be aligned into highly ordered geometries, which is a characteristic central to the construction of integrated circuits. To date, NWs have been used to build nanoelectronic devices, such as FETs and p-n diodes, circuit units, including simple logic gates, ring oscillators, multiplexers/demultiplexers, and addressable nonvolatile memories, and even nanoprocessors [5–9
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