Noise Sources in Polycrystalline Silicon Thin-Film Transistors
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Noise Sources in Polycrystalline Silicon Thin-Film Transistors Il Ki Han, Young Ju Park, Woon Jo Cho, Won Jun Choi, Jungil Lee, Alain Chovet1, and Jean Brini1 Nano Devices research center, Korea Institute of Science and technology, Seoul, 130650, Korea 1 IMEP, INPG/CNRS, Grenoble, 38016, France ABSTRACT Sources for low frequency noise in polycrystalline silicon thin-film transistors are analytically investigated. The grain boundary is modeled as symmetric Schottky barrier and a new device equation for current conduction in thin-film transistors is presented. At lower currents where barrier height is large enough to provide necessary distribution of time constants for 1/f noise, the number fluctuation via barrier height modulation at the grain boundary is found to be the main noise generation mechanism. At higher currents, mobility and diffusivity fluctuation are found to be dominant INTRODUCTION Low frequency excess noise or 1/f noise in polycrystalline silicon thin-film transistors (poly Si TFT’s) limits the device performance when the transistors are used as switching devices. 1/f noise measurements can also provide a spectroscopy tool for the defects related device structure and sometimes provide more information than other techniques such as current-voltage analysis, and capacitance-voltage analysis. Recently, there has been a lot of research to enlarge the grain size and reduce the defect density [1-4], since the characteristics of poly Si TFT’s are significantly affected by the grain size and the defect density. Grain boundary is known to be the leading part in the generation of noise. Different models for 1/f noise in poly Si thin-film resistors or TFT’s were developed. Mobility and diffusivity fluctuation model was first developed based on the model for Schottky diodes for low and moderately doped poly Si films and transistors [5]. For highly doped thin films, thermal noise due to dielectric losses in the grain boundary was also considered [6]. Carrier number fluctuation model for conventional crystalline Si MOSFET’s [7] was attempted to explain the drain current dependence of the noise intensity but with extraordinarily high oxide trap state density [8]. Barrier height inhomogeneity was taken into account to provide the necessary distribution of time
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constants for 1/f noise, which might be justified in small grain samples with a wide distribution of barrier heights [9]. In this paper we discuss possible noise sources for poly Si TFT’s and propose a new model successfully explaining the general feature of the experimentally observed current dependence of the noise current density [10]. In the model we also present a new device equation based on symmetric Schottky barrier (SSB) model for the grain boundary. Number fluctuation mechanism, in particular the thermal activation is employed as well as the mobility and diffusivity fluctuation. For simplicity we consider the case of a poly Si TFT with single grain boundary in the channel, which can be easily generalized to multi grain boundary cas
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