Optimal thickness for Si interlayer as diffusion barrier at the Si 3 N 4 /GaAs interface: A transmission electron micros
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D. S. L. Mui and H. Morkoc Science Engineering Laboratory, and Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801-3080 (Received 23 March 1994; accepted 19 January 1995)
Using transmission electron microscopy, we investigate Si3N4 grown in situ on GaAs metal-insulator-semiconductor (MIS) device structures with a Si interlayer, which has been previously shown to improve the electrical properties of field-effect transistors with Si3N4 gates on GaAs. We find that the primary role of the Si interlayer is to prevent the reaction between the nitride or nitrogen used for growth and GaAs. The interlayer thickness dependence of this microstructure, and its relationship to electrical properties, are discussed. The optimal thickness of the thin pseudomorphic Si interlayer appears to be around 0.4 nm. The growth temperature dependence of the critical thickness for morphological instability is demonstrated.
I. INTRODUCTION Si metal-oxide-semiconductor (MOS) devices are the basis for most modern electronics. In comparison, GaAs MOS devices have not been as successful. The main reason for this is the poor properties of GaAs oxides, a mixture of Ga 2 O 3 and As 2 O 3 . As 2 O 3 is not stable against the solid-state reaction 2GaAs + As 2 O 3 —• Ga 2 O 3 + 4As. 12 Even though Ga 2 O 3 is stable on GaAs, its formation leaves free As on the GaAs surface. These free As precipitates are believed to be responsible for interface or surface states that pin the Fermi level and degrade device properties.3-4 (Also, a Ga 2 O 3 film is porous and leaky, and fails to protect the GaAs surface from further oxidation in atmosphere and the outdiffusion of Ga and As atoms from the GaAs surface.3) Because of these poor properties of the (native oxide)/GaAs interface, some workers have tried to use other insulators, such as SiO 2 , 5 A1N,6 and Si 3 N 4 , 8 as gate insulators for metal-insulator-semiconductor field-effect transistors (MISFET) based on GaAs. Because of the morphology of the GaAs surface, GaAs MIS structures are generally characterized by a high density of interface states which pin the interface Fermi level. There are several models to explain the origin of these interface states, for example, the unified disorder-induced gap state (DIGS) model claims that the gap states at the MIS interfaces come from incomplete separation of bonding and antibonding states of local bonds due to random 1126
J. Mater. Res., Vol. 10, No. 5, May 1995
http://journals.cambridge.org
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stress, resulting from bond mismatch between semiconductor and insulator.9"11 Another important issue for control of the interface structure in the GaAs MIS device is the condition of the GaAs surface; As-rich surfaces are found to be very stable.12 To reduce surface or interface states, many surface treatment techniques, such as photochemical oxidation,3 sulfur treatment,4 HC1 treatment,5 AsH 3 , H 2 , TMG (trimethylgallium) treatment,6 and nitrogen passivation13 have been reported. Recently, several grou
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