Optimization of Ion Implantation processes for 4H-SiC DIMOSFET
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Optimization of Ion Implantation processes for 4H-SiC DIMOSFET N. Piluso1, E. Fontana1, M.A. Di Stefano1, G.Litrico2, S. Privitera2, A. Russo1, S. Lorenti1,, S.Coffa1, F. La Via2 1
STMicroelectronics, Stradale Primosole, 50, 95100 Catania, Italy. 2
IMM-CNR, VIII Strada, 5, 95121 Catania, Italy.
Abstract In this paper the defects generated by ion implantation in 4H-SiC DIMOSFET (Double Implanted MOSFETs), and their evolution after annealing process, have been studied in detail. The point defects generated by the source or body implantation process have been detected by micro-photoluminescence (µPL) and the effect of these defects on the electrical characteristics of the DIMOSFET has been studied. The role of the annealing process has been carefully investigated by using different temperatures. It appears fundamental for the restoring of the crystal damage. The effect of the ion implantation dose has been investigated as well. By reducing the source ion implanted dose a large decrease of point defects has been detected and a considerable improvement of the electrical characteristic of the DIMOSFET has been observed. Introduction Ion implantation processes are believed to be fundamental for the success of 4H-SiC DIMOSFET devices, since determine the on resistance value and may affect the defect density and the channel mobility. The implantation dose and the activation temperature are therefore two crucial parameters that need to be studied in detail. Indeed, ion implantation at high dose generates a detrimental disorder in the lattice crystal that cannot be easily restored by the annealing process. On the other hand, a low dose may affect the performance, by increasing the resistivity of the device. In this work the ion implantation dose, as well as the activation temperature, have been fine tuned in order to optimize the electrical characteristics of MOSFET devices. The on-resistance of a power MOSFET naturally consists of a series connection of several resistances, such as the source resistance, the channel resistance, the drift layer resistance, and the substrate resistance. In DIMOSFETs (Double Implanted MOSFETs) the resistance between two neighboring p-wells (JFET resistance) cannot be neglected and, with the channel resistance, it is the dominant factor in the SiC DIMOSFET devices with blocking voltages up to about 2-3 kV. [1] Then a considerable amount of work has been done from several research groups to try to increase the channel mobility and subsequently reduce the channel resistance. Another important issue of the DIMOSFET structure is the implantation-induced damage. In fact, in this structure, both the body and the source are implanted and the defects introduced by the implantation process can strongly affect the electrical characteristics and the reliability of these devices. The quality of the SiO2 /SiC interface is significantly lower when the oxide is grown on ion-implanted material. The field-effect mobility reported for ion-implanted devices is highly dependent on the doping concentration and is
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