Optimization of poly-silicon process for 3C-SiC based MOS devices
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1246-B06-04
Optimization of poly-silicon process for 3C-SiC based MOS devices R. Esteve1,2, A. Schöner1, S.A. Reshanov1, C.-M. Zetterling2 1
ACREO AB, Electrum 236, SE-164 40 Kista, Sweden
2
Department ICT, KTH, Electrum 229, SE-164 40 Kista, Sweden
ABSTRACT The electrical properties of wet oxides with poly-silicon gates fabricated on n-type 3C-SiC (001) epilayers have been studied. Five alternatives have been considered for the activation of the poly-silicon layer. The influence of two main parameters has been thought-out: the process type (thermal annealing or rapid thermal annealing) and the gas species composing the annealing atmosphere (argon, dry or wet oxygen). The poly-Si activation process combining RTA and argon as ambient demonstrates minimal thermal budget and superior preservation of the oxide quality. The fabricated MOS structures demonstrate high electrical properties and reliability of the oxide. That results in a small negative flat band voltage shift of -0.9 V and in an interface state density Dit of 7.4 × 1010 eV-1cm-2 at 0.63 eV below the conduction band. The TZDB measurements revealed an average breakdown electric field of 9.4 MV/cm. INTRODUCTION Cubic 3C-SiC is regarded as a perfect material for medium power MOSFETs with blocking voltages of around 1500V and current handling of 100A and more. One of the main issues to realize such power MOSFETs is the improvement of the gate oxide to ensure low on-state operation. The benefits of the implementation of an advanced oxidation process combining PECVD (Plasma Enhanced Chemical Vapor Deposition) SiO2 deposition and short post-oxidation steps in wet oxygen has been previously demonstrated [1]. The concentrations of fixed and mobile charges in the oxide and at the SiO2/SiC interface were significantly reduced. Silicon technologies have indicated earlier the benefits of poly-silicon gate for MOS devices. Significant improvements in terms of gate oxide reliability were achieved [2-6]. To avoid the desorption of hydrogen atoms used for the passivation of defects in 3C-SiC based oxides, the deposition and activation processes of poly-Si for 3C-SiC MOS devices should describe a minimal thermal budget. Such reduced thermal budget should help to preserve the high electrical properties of the oxide. In this study we report on the influence of the poly-silicon activation process on the electrical properties of 3C-SiC MOS structures. The influence of two main parameters has been considered: the type of the process i.e. thermal annealing (TA) or rapid thermal annealing (RTA) and the gas species composing the annealing atmosphere (argon, dry and wet oxygen). EXPERIMENT MOS capacitors were fabricated on free-standing n-type 3C-SiC (001) wafers, which had a 5µm thick epitaxial layer doped with nitrogen to a concentration of 5×1015 cm-3. We have
prepared five sets of samples (see Fig. 1). Gate oxides were fabricated by PECVD deposition of SiO2 from SiH4 and N2O precursors (45s, 300°C) followed by a post-oxidation at 950°C for 3 h in wet oxygen (O2+H2O) under a
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