Oxide Electrodes for Buried-Channel Field Effect Transistors
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Oxide Electrodes for Buried-Channel Field Effect Transistors A.G. SCHROTT*, J.A. MISEWICH*, D.W. ABRAHAM*, R. RAMESH**, V. NAGARAJAN** *IBM Research, T.J. Watson Research Center, Yorktown Heights, NY 10598. **Materials Research Science and Engineering. Center, University of Maryland, College Park, MD 20742 ABSTRACT In this paper we describe the fabrication of oxide based electrodes that allow epitaxial growth of multilayer structures used to fabricate buried oxide-channel field effect transistors. The distinct characteristic of our buried electrodes is that they provide an etch stop layer which allow the opening of vias through the gate oxide using chemical etching. They can be patterned to define 1 µm channel lengths and exhibit low contact resistance with channel materials such as YxPr1-xBa2Cu3O7-δ (YPBCO) or YBa2Cu3O7-δ (YBCO) . INTRODUCTION The second generation of oxide channel field effect transistor (OxFET) architecture with a buried channel [1,2] provides a solution to several of the limitations present in the first generation of OxFets,[3] and offers the potential to scale beyond the limits of silicon technology. Both first and second architectures are shown schematically in Figs. 1a and 1b, respectively. In the buried channel architecture, the substrate is typically nonconducting undoped strontium titanate (STO), or Lanthanum aluminate (LAO) and the cuprate channel is now directly on the atomically smooth substrate ensuring a higher quality channel film. The latter is also protected from moisture by the gate oxide layer. The source and drain electrodes make contact with the cuprate material at the gate oxide/channel interface reducing the potential series resistance. Since the cuprate is protected from moisture by the gate oxide layer, the cuprate channel layer can eventually be made thinner, thereby reducing the potential parallel resistance. Also, since the substrate is insulating the large gate capacitance and coupling capacitance to other devices is eliminated. In the latter devices the gate oxide/channel interface quality and gate oxide dielectric strength are critical to their performance. In addition, the chemical compatibility between the source and drain materials, and the channel film is critical to minimize contact resistance. In the first generation devices the source and gate electrodes are evaporated at room temperature on top of the channel film and therefore no significant contact resistance arise. In the buried channel structures, however, the channel film is grown in an oxygen atmosphere by pulsed laser deposition (PLD) with the substrate and the already defined electrodes held at temperatures higher than 500 o C (typically around 700 o C).[1,2] Although the devices built with Pt electrodes and La2CuO4 (LCO) do not exhibit contact resistance problems, when YBCO or YPBCO are used, large contact resistances, in the MΩ range, are observed and make these devices impractical. This fact is consistent with the problems typically found at the contacts between metals electrodes and high temperatur
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