Phase Change Memory with Chalcogenide Selector (PCMS): Characteristic Behaviors, Physical Models and Key Material Proper
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1250-G14-01-H07-01
Phase Change Memory with Chalcogenide Selector (PCMS): Characteristic Behaviors, Physical Models and Key Material Properties I. Karpov, D. Kencke, D. Kau, S. Tang*, and G. Spadini Intel Corporation, 2200 Mission College Blvd., Santa Clara, California 95054 *Numonyx B.V. , 2550 N. 1st Street, Suite 250, San Jose, CA 95131
ABSTRACT We present a novel scalable and stackable nonvolatile solid state memory. Each cell consists of a storage element, based on phase change memory (PCM) element, and an integrated selector, using an Ovonic threshold switch (OTS). The cell is implemented to enable a true cross-point array. The main device characteristics and behaviors, corresponding physical processes in different operation modes, and key material properties are discussed.
INTRODUCTION The chalcogenide phase change device utilizes electrically initiated reversible amorphous-to-crystalline phase changes in multi-component chalcogenides, such as Ge2Sb2Te5, whose significantly different phase resistances are used as the two logic states [1]. For each PCM element in the array a selector element is required to avoid a parasitic path in the resistive network In this work, a thin-film two-terminal threshold switch, OTS, [2,3] is used as the selector for PCM arrays [4]. In contrast to PCM, the composition of chalcogenide material in the switch is selected [2,3] to maintain its amorphous/glassy state regardless of applied pulse characteristics. The switch is integrated with a PCM element to form the PCMS device and isolate individual PCM cells in the cross point array. EXPERIMENT PCMS cell and memory array are shown in Fig. 1a and 1b, respectively. The vertical stack of a PCMS cell consists of OTS and PCM elements interlinked by a middle electrode, with a top electrode connecting OTS to bit line (column) above and a bottom electrode contacting PCM below to the word line (row). The memory cell stack, including rows and columns, can be sandwiched between back end layers and fully integrated with a CMOS technology.
Fig. 1. (a) SEM of PCMS cell. (b) PCMS cross-point array, sandwiched between M2 and M3 metal layers in the back end of the process, and integrated with CMOS technology [4] As illustrated in Fig. 1(a) PCMS cell consist of two devices, PCM and OTS, in series. These devices may be fabricated for characterization by leaving out either the PCM or the OTS layer. The I-V characteristics of individual PCM and OTS cells, fabricated by dedicated process flows, are shown in Fig. 2(a) and 2(b), respectively. Note that a SET or RESET programming pulse changes the memory state of the PCM device but does not change IV characteristic of the OTS device.
Fig. 2. (a) Typical I-V characteristics of a dedicated PCM cell in SET (left) and RESET (right) states. (b) Typical I-V characteristics of the OTS cell after experiencing SET (left) and RESET (right) pulses.
PCMS cell I-V characteristics are shown in Fig. 3. SET and RESET states have different threshold voltages. The SET state has lower threshold voltage than the RESET
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