Pioneering Application of Corona Charge-Kelvin Probe Metrology to Noncontact Characterization of In 0.53 Ga 0.47 As/Al 2
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Pioneering Application of Corona Charge-Kelvin Probe Metrology to Noncontact Characterization of In0.53 Ga0.47 As/Al2O3/HfO2 Stack Alexandre Savtchouk1, John D’Amico1, Marshall Wilson1, Jacek Lagowski1, Wei-E Wang2, Taewoo Kim2, Gennadi Bersuker2, Dmitry Veksler2, and Donghyi Koh2 1 2
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ABSTRACT We report the first successful application of corona charging noncontact C-V and I-V metrology to interface and dielectric characterization of high-k/III-V structures. The metrology, which has been commonly used in Si IC manufacturing, uses incremental corona charge dosing, QC, on the dielectric surface, and the measurement of surface voltage response, VS, using a Kelvin-probe. Its application to In0.53Ga0.47As with a high-k stack required modifications related to the effects of dielectric trap induced voltage transients. The developed Corona Charge-Kelvin Probe Metrology adopted strictly differential measurements using QC and V, and corresponding differential capacitance rather than measurements based on total global charge, Q, and voltage, V, values. Electrical characterization data including interface trap density, electrical oxide thickness, and dielectric leakage are presented for a sample containing an In0.53 Ga0.47 As channel overlaid with a bilayer (2nm Al2O3/5nm HfO2) dielectric stack that is considered to be very promising for application in performance NFETs with high-mobility channels.
INTRODUCTION III-V materials are forecasted to be introduced in CMOS technology as high mobility channel materials [1]. Considerable efforts are being devoted to addressing the fundamental material challenges. Full realization of III-V high mobility channel advantages involves gate stack scaling, e.g. reducing the gate dielectric thickness [2] without an inordinate increase in gate leakage. High-k dielectric stacks, such as the Al2 O3/HfO2 stack studied in this work, are promising candidates to fulfill the gate dielectric requirements [3]. However, the complexity of high-k/III-V electrical characterization is apparent when one considers the fundamental differences of III-V materials compared to traditional Si CMOS. One of the most significant technological challenges presenting a major issue for the implementation of high mobility III-V semiconductors is the highly disordered high-k/III-V interface. Interface defects affect both device performance [4,5,6] and reliability [7]. A conventional figure of merit for the interface quality is the interface state density (Dit). However, determination of Dit in high-k/III-V stacks presents a difficult task due to specific properties of the high mobility III-V channel materials, such as InGaAs [8,9]. Namely these properties are: (i) a low density of states (DOS) in the conduction band (two orders of magnitude lower compared to Si); and (ii) a narrow bandgap, leading to significant generation of minority carriers at room temperature. One of the basic problems fo
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