Performance Investigation of Silicon-on-Insulator Junctionless Drain Extended FinFET for High Power, Radio Frequency App
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ORIGINAL PAPER
Performance Investigation of Silicon-on-Insulator Junctionless Drain Extended FinFET for High Power, Radio Frequency Applications Ajay 1 Received: 1 October 2020 / Accepted: 20 November 2020 # Springer Nature B.V. 2020
Abstract This research article explores the scope of Silicon-On-Insulator (SOI) Junctionless (JL) Drain Extended (De) FinFET and compared it with Conventional SOI Drain Extended FinFET (Conv. SOI DeFinFET) for high power and high frequencies applications. The device simulation is performed by three dimensional (3D) simulations by sentaurus TCAD tool to optimize the device parameters at 14 nm gate length including the height (Hfin), the width (Wfin) and channel doping (Nch) of the fin of both devices. Both devices are compared in terms of drain current (DC) characteristics (breakdown voltage, on-resistance and drain current) and radio frequency (RF) characteristics (trans-conductance, current gain, cut-off frequency, power gain and maximum operating frequency). The results reveal that the proposed JL SOI DeFinFET is also one of the contenders with Conv. SOI DeFinFET for the regime of high power and high frequency. Keywords Cut-off frequency . Drain extended FinFET . SOI Junctionless DeFinFET . Radio frequency . Trans-conductance . Maximum operating frequency
1 Introduction In past three decades, the aggressive efforts have been taken by CMOS design industry to achieve cost-effective fabrication, high speed and low-power consuming semiconductor devices. The down scaling of CMOS device parameters is a wonderful approach to achieve above mentioned requirements and enhance the device performance [1]. Continues, down scaling encounter short-channel effects (SCEs), namely drain induced barrier lowering, threshold voltage roll-off, hot carrier, velocity saturation, impact ionization and sub-threshold swing which seriously affect the device behavior [2–5]. Several solutions have been presented by CMOS design industry to improve the SECs from the devices likewise halo doping, super-steep retrograde channel doping, shallow source drain extensions, high-K dielectric replacing the gate oxide and metal gates instead of poly gates [6–8]. Further, CMOS design industry investigated several multi-gate
* Ajay [email protected] 1
Advanced Nanoelectronic Device & Circuit Characterization Research Group, Department of Electronics System Engineering, Indian Institute of Science, Bangalore 560012, India
structures to improve the gate controllability such as Double Gate MOSFET, Surrounding-Gate/Gate All Around (SG/ GAA) MOSFET, nanowires, nanotubes and FinFETs. However, before mentioned devices have back to back two p-n junctions becomes more prominent as a weakness. The fabrication of a highly precise junction in nanoscale regime poses a great difficulty [9–13]. The above mentioned technological issue has been removed in newly invented Junctionless MOSFET which has no counter doped metallurgical junctions [14–16]. Unlike conventional MOSFETs, JL MOSFET has single doping species at the same concentrati
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