Process Optimization and Integration of HFO 2 and HF-Silicates

  • PDF / 1,628,250 Bytes
  • 12 Pages / 612 x 792 pts (letter) Page_size
  • 119 Downloads / 226 Views

DOWNLOAD

REPORT


D7.6.1

PROCESS OPTIMIZATION AND INTEGRATION OF HFO2 AND HF-SILICATES Hideki Takeuchi and Tsu-Jae King Department of Electrical Engineering and Computer Sciences University of California, Berkeley Berkeley, CA 94720-1770, U.S.A.

ABSTRACT We have established in-line characterization techniques for analyzing the bulk and interface-charge properties of dielectric films, for process optimization. Surface charge analysis (SCA) is used to determine the densities of interface states, fixed charge, and near-interface traps in ultra-thin dielectrics, and is useful for tracking the influence of post-deposition processing on interface-charge properties. Spectroscopic ellipsometry (SE) is used to obtain the absorption spectra in the conduction band-tail region. The intensity of an extra absorption peak inside the bandgap of HfO 2 is clearly correlated with leakage current density and near-interface trap density. Based on the observed process dependencies, defects within the HfO 2 films are likely to be oxygen vacancies. The relative scalability of HfO2 and Hf-silicate films of various compositions is examined using a figure of merit based on the direct-tunneling leakage current model. Pure HfO2 is expected to be more scalable than Hf-silicates. However, it is typically accompanied by an interfacial layer which significantly increases the equivalent oxide thickness (EOT). A 20% Hf silicate with relative permittivity of 11 or higher can be more scalable than HfO2 with an interfacial layer. Alternatively, an ultra-thin interfacial Si3N4 diffusion barrier can be used with HfO2, to allow for more aggressive EOT scaling. The dependencies of interfacecharge properties and surface roughness on the nitride barrier formation process are presented.

INTRODUCTION The scaling of conventional SiO2-based gate dielectrics with transistor gate length is reaching physical limits. Although bulk-Si complementary metal-oxide-semiconductor fieldeffect transistors (CMOSFETs) with physical gate length down to 5 nm have been demonstrated by research groups using SiO2 as the gate dielectric [1], high-permittivity (high-κ) gate dielectrics will be necessary for CMOS production beyond the 65 nm technology node, in order to achieve adequately low gate current density [2]. Through many research efforts in past years, the candidate high-κ materials have been narrowed down to hafnium (Hf)-based dielectrics for several reasons. First, HfO 2 is one of a few metal oxides that are predicted to have good thermal stability in contact with Si, from thermodynamic calculations [2]. Transistors with HfO 2 gate dielectrics have been successfully fabricated using a conventional CMOS process flow with either poly-Si [3,4] or metal [5,6] as the gate material, and they yield lower gate leakage current density as compared against SiO 2 devices with the same areal gate capacitance. The low diffusivity of Hf in Si is also very attractive; Hf diffusion into Si from Hf0.42Si0.58O2 was found to be less than 0.5-1.0 nm, even after furnace annealing at 1100oC for 6 minutes [7]. Ho