The Influence of Defects on Compatibility and Yield of the HfO 2 -PolySilicon Gate Stack for CMOS Integration
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The Influence of Defects on Compatibility and Yield of the HfO2-PolySilicon Gate Stack for CMOS Integration V.S. Kaushik, S.DeGendt1, R.Carter1, M.Claes1, E.Rohr1, L.Pantisano1, J.Kluth, A.Kerber, V.Cosnier, E.Cartier, W.Tsai, E.Young, M.Green, J.Chen, S-A.Jang, S.Lin, A.Delabie1, S.V.Elshocht1, Y.Manabe1, O.Richard1, C.Zhao1, H.Bender1, M.Caymax1, M.Heyns1 International Sematech, 2706 Montopolis Drive, Austin Texas 78741 & 1 Inter-university MicroElectronic Center (IMEC), Kapeldreef 75, 3000 Leuven, Belgium. ABSTRACT Hafnium-based dielectrics are under wide consideration for high-K gate dielectric applications. Since the gate electrode typically used in CMOS integration consists of polysilicon with n- or p-type dopants, compatibility of the HfO2 layer with the polySi deposition and dopant activation steps is critical. Capacitors were fabricated with HfO2 films deposited by ALD and MOCVD, and using polysilicon gate electrodes deposited by CVD processes. These devices showed leakage failures with yields that were observed to depend on the area, dielectric thickness and annealing conditions during the process. Investigation of the root cause of these leakage failures suggested that the leakage failures may be caused by a defect-related mechanism. The implication of this is that the leakage occurs at localized ‘defect’ sites rather than broadly through the HfO2 layer. Emission microscopy analysis and physical characterization of the HfO2 film were used to corroborate the proposed model. Defect density was observed to be strongly dependent on the processing of the dielectric film. In order to make Hf-based dielectric stacks compatible with polysilicon for conventional CMOS transistor integration with acceptable yield, further postdeposition treatment may be necessary to eliminate or cure the defects. INTRODUCTION: Hafnium-based materials such as oxides, silicates and aluminates of hafnium are being widely studied for applications as high-K gate dielectric to meet the needs of CMOS scaling. The gate electrode that is used in typical CMOS integrated circuit processing is polysilicon with n- or p-type dopants. For rapid deployment of high-K gate dielectrics into existing CMOS lines, compatibility of the high-K dielectric with conventional polysilicon deposition processes is critical. It is therefore necessary to evaluate the stability of the high-K gate dielectric layer during polysilicon deposition and during subsequent processing. This typically involves annealing the gate stack for activation of dopants within the polysilicon gate electrode. The polysilicon process module needs to be optimized for CMOS application with respect to poly depletion, boron penetration and stability at activation temperatures. Previous studies [1] on integration of ZrO2 gate dielectric with CVD polysilicon showed the formation of Zr-silicide. This resulted in high leakage failures thereby limiting the applicability of ZrO2 with polysilicon and shifting the focus to HfO2. Although silicides of Hf have not been reported in HfO2-
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