A Multiplierless DC-Blocker for Single-Bit Sigma-Delta Modulated Signals
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Research Article A Multiplierless DC-Blocker for Single-Bit Sigma-Delta Modulated Signals Amin Z. Sadik,1 Zahir M. Hussain,1 and Peter O’Shea2 1 School 2 School
of Electrical and Computer Engineering, RMIT University, Melbourne, Victoria 3001, Australia of Engineering Systems, Queensland University of Technology, Brisbane, Qld 4001, Australia
Received 11 February 2006; Revised 29 July 2006; Accepted 10 September 2006 Recommended by Roger Woods The DC content in single-bit domain is both undesirable and hard to remove. In this paper we propose a single-bit multiplierless DC-blocker structure. The input is assumed to be sigma-delta modulated bitstream. This DC-blocker is designed using a delta modulator topology with a sigma-delta modulator (SDM) embedded in its feedback path. Its performance is investigated in terms of the overall signal-to-noise ratio, the effectiveness of DC removal, and the stability. The proposed structure is efficient for hardware realisation. Copyright © 2007 Amin Z. Sadik et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
1.
INTRODUCTION
Single-bit systems possess very attractive properties as compared to their multi-bit counterparts. The single-bit implementation produces relatively higher performance and lower hardware complexity. Several relevant previous works have studied and proposed different single-bit structures (e.g., [1– 5]). Unfortunately, the design in the single-bit domain has been suffering from two obstacles. First, there are still several unresolved problems such as the adaptivity and stability [6]. Second, the design itself is not straightforward as in multibit techniques. However, we do expect that, ultimately, these pitfalls would be tackled in no far future, and the single-bit or at least the short word-length signal processing (DSP) systems would become very popular [7]. A DC component can be introduced upon a DC-free signal at various stages in the signal bitstream by analogto-digital conversion or by truncation in fixed-point systems. This DC bias is unwanted in DSP applications as it reduces the dynamic range of the system and can drive the system into saturation. Moreover, a DC-biased bitstream has a highly undesired impact on the performance of the singlebit system, as the DC content bears no information and enhances unwanted limit cycles (which may in turn affect system stability). In this paper, we propose an efficient single-bit DCblocker that contains no multi-bit multiplier and would be
very simple to be realised using direct hardware implementation or Field programmable gate arrays. 2.
DESIGN AND ANALYSIS
A simple multi-bit DC-blocker can be seen in [8]. The transfer function of a traditional infinite precision IIR DCblocking filter is H(z) =
1 − z−1 . 1 − ζz−1
(1)
The DC cancellation is due to the transfer function having zero at z = 1 (0 Hz). The pole at z = 1 − ζ adjusts the system band
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