A Novel n -Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme
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A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme K. Saranya1 · K. N. Vijeyakumar2 Received: 26 February 2019 / Revised: 10 September 2020 / Accepted: 13 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Reversible logic has been emerging as a replacement for conventional digital computers and has been found to be a promising technology for the future that can improve the quality of circuits in terms of power, speed, heat dissipation, life span, and input traceability. The new generation of quantum processors demands the efficient implementation of decimal data path elements in many commercial, financial, and Internet-based applications. Reversible binary-coded decimal multipliers are among the important circuits in quantum computers. In this approach, we propose a lowpower reversible radix binary-coded decimal multiplier. The proposed methodology uses a novel 4221 reversible recorder gate to select precomputed constant multiples and binary to excess-six conversion reversible decimal adder for partial product compression. The proposed multiplier is designed with 180-nm application-specific integrated circuit technology using the Cadence EDA tool and is compared with state-of-the-art BCD algorithms designed using reversible gates. Experimental evaluations revealed that the proposed design demonstrates power and power-delay product reductions of 28% and 37%, respectively, compared to those of the best BCD algorithms implemented in reversible logic. Keywords Radix recoder · Reversible gates · Quantum application · Decimal multiplier
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K. Saranya [email protected] K. N. Vijeyakumar [email protected]
1
Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Coimbatore, India
2
Department of Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Coimbatore, India
Circuits, Systems, and Signal Processing
1 Introduction In conventional computers, information loss leads to more power and heat dissipation problems. In the 1960s, Landauer [12] stated that conventional computation, irrespective of the realization methodology, would result in high energy and information loss. He also proved that each bit of information lost is accompanied by KTln2 joules of energy loss. Bennett [2] showed that a circuit must be constructed using a reversible logic gate to avoid KTln2 joules of energy dissipation. In recent years, reversible logic has been used in various areas of quantum computation [14, 16], DNA computation, etc. The multiplier is a very important component in high-performance computing systems such as digital filters, microprocessors, and digital signal processors. A system’s performance is mostly dependent on the multiplier because the multiplier is generally the time-consuming component among the various data path elements. A number of approaches to designing full-width [11], fixed-width [21–23], and approxim
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