A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching
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A Technique for Source/Drain Elevation using Implantation Mediated Selective Etching M. Q. Huda, and K. Sakamoto Nanoelectronics Research Institute National Institute of Advanced Industrial Science and Technology Central 2, 1-1-1 Umezono, Tsukuba 305-8568, Japan Email: [email protected] ABSTRACT A process involving implantation mediated selective etching has been developed for Source/Drain elevation of CMOS devices. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO2 structure by chemical vapor deposition (CVD) at 700 °C. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical channeling direction. A short duration post-anneal at 420 °C was used for structural recovery of the silicon layer. Polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits. INTRODUCTION Selective elevation of silicon on patterned structures has been studied for a long time [1]. The prospective application is on elevated source/drain (ESD) structures in ULSI technology [2]. The elevated source/drain regions in complementary metal-oxide-semiconductor (CMOS) devices provide the extra silicon thickness that allow the formation of silicide contacts for very shallow junctions. An ESD structure is equally important for fully depleted silicon-on-insulator (FDSOI) CMOS devices. The additional thickness of silicon is essential to ensure that the source/drain region is not fully consumed by silicides during the alloying process. The main challenge in ESD is the selective elevation of silicon layer without having any deposition on the isolation material and sidewall spacers. Any deposition on these insulating layers in the form of polysilicon results in a silicide short circuit (bridging) during the self aligned silicide (SALICIDE) process. Selective Epitaxial Growth (SEG) by chemical vapor deposition (CVD) is commonly used in ESD formation [2-6]. A presence of Si-H-Cl environment is normally used to maintain a selectivity between deposition rates on silicon and the insulating layer. However, thickness of silicon layer formed by SEG is limited by the onset of polysilicon nucleation on insulating layers. Variation of SEG-Si thickness over the surface has also been reported [3,4]. In addition to thickness related problems, the SEG technique has a serious shortcoming of forming (111) and (311) facets along the pattern edge [5]. These facets result in thin or almost negligible elevation of source/drain region near the gate sidewall. This seems to be a bottleneck in the SEG technique as the source/drain metallization, and also the junction tends to be deeper along the gate sidewall, causing additional leakage and short channel effects, res
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