Active Si Interposer : Combination of Through-Si Vias and Redistribution
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0970-Y05-03
Active Si Interposer : Combination of Through-Si Vias and Redistribution Kazumi Hara, Nobuaki Hashimoto, Haruki Ito, Yoshihiko Yokoyama, and Tsuyoshi Imamura Advanced Technology Development Center, Seiko Epson corporation, SUWA MINAMI Plant 1010 Fujimi,Fujimi-machi, Suwa-gun, Nagano-ken, 399-0295, Japan ABSTRACT Active Si Interposers (ASI), which are device chips with through Si vias (TSVs) and redistribution wirings, are the focus of this study. A feature of the module is that the redistribution layer includes a stress buffer layer so that stress can be alleviated when it is mounted on a motherboard. For the purpose of this study, it was decided to conduct the process from the backside of the wafer for efficiency of production. One feature of this process is that a device wafer was processed with a glass wafer supported throughout the TSVs’ process in order to facilitate process of a thin wafer. However, the maximum temperature of each process was limited. We addressed this problem by the optimization of some of the equipment and the modification of the adhesive that attaches the device wafer to a glass wafer. Finally, a module that was a combination with the ASI and a certain device operated normally. In the last part of this study, the results of the evaluation that studied the impact on the devices of the TSVs’ process are presented. INTRODUCTION As is known widely in the electrical packaging area, through-Si vias technology enables usage of the backside of chips as mounting areas, as well as shortening the wiring length. They provide extremely smaller packages and better transmission efficiency. Until recently, this was merely an issue confined to the field of research and development. However, due to significant advances reported in the last year, it may be not an exaggeration to say that the application of this technology to mass production will eventually occur. Typical products to which through-Si vias technology could be applied are memory stacks and CCD modules [1-4]. Their function can be greatly enhanced in size by applying Through-Si Vias technology compared to packages assembled by existing technologies. However, we can expect further expansion in their application. This is due to the fact that an IC chip now has through vias and redistribution wirings, and that an IC chip can serve as an interposer and be connected to various types of devices in a package. In other words, the device chip is no longer part which is mounted on a board, but an interposer that is a structural necessity as a composition of SiP. Technically, that can be attained by combining through-Si vias with redistribution wirings, called an “Active Si Interposer” (ASI). According to this idea, our model of the ASI was studied. In addition to the features mentioned above, we determined to add a stress buffer layer in order to secure good performance of reliability when combined with devices made of various kinds of materials. In that sense, the function as an interposer was enhanced in our model. Concretely speaking, we pu
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