Adhesion Strength Evaluation of Low-k Interconnect Structures Using a Nanoscratch Method
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Adhesion Strength Evaluation of Low-k Interconnect Structures Using a Nanoscratch Method Jiping YE, Kenichi Ueoka, Nobuo Kojima, Junichi Shimanuki, Miyoko Shimada1 and Shinichi Ogawa1 Research Department, NISSAN ARC, LTD., 1 Natsushima-cho, Yokosuka 237-0061, Japan 1 Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba 305-8569, Japan ABSTRACT A convenient nanoscratch method was combined with atomic force microscope (AFM) and transmission electron microscope (TEM) observations to conduct the first-ever evaluation of the adhesion strength of a complicated microstructure Cu/Ta/TaN/pSiO2/low-k/SiC/pSiO2/Si-substrate with the aim of correlating the fracture strength with the results of chemical mechanical polishing (CMP) tests. Concretely, this evaluation focused on the fact that specimens having a low-k layer pretreated with rare-gas plasma prior to the deposition of the SiO2 layer exhibited low delaminated densities in the Cu CMP process. It was found that a specimen with the rare-gas plasma pretreatment exhibited a higher friction coefficient, a higher critical load and brittle adhesive failure resulting from delamination at the interface between the low-k and SiC layers. A specimen without the rare-gas plasma pretreatment displayed a lower friction coefficient, a lower critical load, and ductile cohesive failure in the low-k layer. Because less plastic deformation was observed in the low-k layer subjected to the rare-gas plasma pretreatment, it is assumed that the pretreatment reinforced the mechanical properties of the low-k layer, making it more resistant to ductile cohesive failure. These results agreed with the CMP test data and indicated that the nanoscratch method makes it possible to predict the ability of complicated Cu/low-k interconnect structures to withstand the CMP process. INTRODUCTION Low-k dielectric materials have attracted a great deal of attention for application to multilevel interconnects and packaging structures [1, 2]. Integration of microelectronic components results in various interfaces between the low-k material and inorganic dielectric layers, such as SiO2 and SiC. Thus, two parts with obviously different thermal, mechanical and chemical properties are combined at the interface. Abrupt changes in these properties are likely to cause delamination at the interface, whereas the low mechanical properties exhibited by low-k dielectric materials are apt to cause debonding of the low-k layer during a chemical mechanical polishing (CMP) process. In either event, poor interfacial adhesion will lower the reliability of the interconnect structures. It is important to evaluate the adhesion strength of low-k interconnect structures for screening out unacceptable dielectric materials and optimizing the CMP process conditions. Usually, four-point bending tests and stud pull tests are widely used to estimate thin-film fracture strength [3-5]. The former test involves sandwiching and epoxy-bonding the test layer side of a specimen to a Si backing and then making a pre-notch to faci
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