Backside Analysis of Ultra-Thin Film Stacks in Microelectronics Technology Using X-ray Photoelectron Spectroscopy
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Backside Analysis of Ultra-Thin Film Stacks in Microelectronics Technology Using X-ray Photoelectron Spectroscopy Thomas Hantschel1, Cindy Demeulemeester1, Arnaud Suderie1, Thomas Lacave1, Thierry Conard1, and Wilfried Vandervorst1,2 1
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium.
2
Instituut voor Kern- en Stralingsfysica, K. U. Leuven, Celestijnenlaan 200D, B-3001 Leuven, Belgium. ABSTRACT X-ray photoelectron spectroscopy (XPS) has become increasingly important over the past few years for supporting the development of ultra-thin layers for high-k metal gates. As the analysis depth of XPS is however limited to about 5-7 nm, it would be extremely useful if the analysis could be carried out from the backside using standard silicon wafers. This approach puts extreme requirements on the sample preparation as hundreds of micrometers of bulk silicon have to be removed and one has to stop with nanometer precision when reaching the interface to the ultra-thin layer stack. Therefore, we have developed dedicated procedures for preparing and analyzing samples for backside XPS analysis. This paper presents the developed approach with a focus on sample preparation using plan-parallel polishing, endpoint detection by interference fringes, and selective wet etching. First angle-resolved XPS (ARXPS) analysis results of metal gate stacks demonstrate the power of such backside analysis. INTRODUCTION The introduction of new materials, the use of more complex materials systems and the down-scaling of layer thicknesses in microelectronics technology poses big challenges in the metrology area. The use of ultra-thin layers for high-k metal gates for improved transistor performance requires an analysis technique which is extremely surface sensitive and can provide information about the stack composition, interaction at the interfaces between the different layers and the influence of different processing steps on the stack composition. X-ray photoelectron spectroscopy (XPS) is gaining increasing importance for this task in the last few years. As the analysis depth of XPS is however limited to about 5-7 nm, and to avoid perturbation of the XPS signal from top surface contamination, the possibility to perform the analysis also from the wafer backside is urgently needed in order to gain access to the region of interest. This requires the removal of hundreds of micrometers thick bulk silicon and at the same time one has to stop at the layer of interest with nanometer-scale accuracy. To tackle this enormous challenge, we have developed dedicated sample preparation procedures and applied the backside XPS approach to advanced material systems. The key of the developed method is an optimized procedure for planparallel polishing (extension of tripod-based polishing [1]), the use of interference fringes for thickness measurement and the removal of silicon by selective wet etching. The basic approach for backside analysis has been developed originally for secondary ion mass spectrometry (SIMS) [2,3] but the requirements for backside XP
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