Charge Transport in Pentacene Thin Film Transistors
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Charge Transport in Pentacene Thin Film Transistors J. H. Schön, L. D. Buchholz, Ch. Kloc, and B. Batlogg1 Bell Laboratories, Lucent Technologies, 600 Mountain Ave., Murray Hill, NJ 07974, USA 1 also at : Solid State Physics Laboratory, ETH Hönggerberg, CH-8093 Zürich, Switzerland ABSTRACT The charge transport properties in polycrystalline pentacene thin film transistors is investigated. A potential barrier is formed at grain boundaries due charged trapping states. The influence of such grain boundaries on the hole mobility of the devices is analyzed for different grain sizes, trap concentrations, and carrier densities. The results reveal that room temperature mobilities exceeding 0.5 cm2/Vs can be obtained in thin films with large grains as well as in nanocrystalline material. Consequently, single crystal device limits can be reached also by polycrystalline pentacene thin film transistors.
INTRODUCTION Organic field-effect transistors have emerged as promising devices for low-cost electronics [1-3]. Among all investigated oligomeric and polymeric materials, pentacene has demonstrated the best electrical performance so far. Mobilities exceeding 1.5 cm2/Vs, on/off ratios of > 107, and sub-threshold swings below 1 V/decade have been obtained [4,5]. High switching speeds have been achieved in complementary circuits in combination with amorphous silicon or organic n-channel materials [1,6,7]. In addition, ambipolar operation of single crystalline devices has been obtained and first complementary inverter circuits have been demonstrated [8]. The capabilities and limitations of pentacene devices have been estimated on the basis of single crystal investigations previously [5,8]. In this study, we focus on the influence of extrinsic parameters such as grain boundaries on the device performance of pentacene thin film transistors.
EXPERIMENTAL Pentacene thin films have been deposited from the vapor phase on polyimide substrates in a stream of hydrogen. Details of the experimental technique for single crystal growth have been reported earlier [5]. Depending on the growth conditions (substrate temperature, gas flow, temperature gradient, ...) nanocrystalline material or films with grain sizes up 30 µm have been prepared. Source and drain contacts(on top of the thin films) as well as the gate electrode have been prepared by thermal evaporation of gold through a shadow mask. Typical channel length and width are in the range from 20 to 50 µm and 500 to 2000 µm, respectively. RF-magnetron sputtered amorphous Al2O3 has been used as gate insulator (capacitance Ci ≈ 30 nF/cm2) for these pentacene thin film transistors (TFTs).
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RESULTS AND DISCUSSION Due to active trapping sites at the grain boundary free carriers will be captured. The presence of such charged traps results in the formation of a potential barrier. The barrier height Eb depends significantly on the screening and, hence, on the carrier density p within the film. The data are analyzed using the grain boundary trapping model proposed by Seto [9]. The transport
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