CVD Growth and Passivation of W and TiN Nanocrystals for Non-Volatile Memory Applications
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CVD Growth and Passivation of W and TiN Nanocrystals for Non-Volatile Memory Applications G.Gay1, D.Belhachemi1, J.P. Colonna1, S. Minoret1, A. Beaurain2, B. Pelissier2, M.C. Roure1, D. Lafond1, E. Jalaguier1, G. Molas1, T. Baron2 and B. De Salvo1 1 CEA LETI MINATEC, 17 rue des Martyrs, 38054 Grenoble, France 2 CNRS-LTM, 17 rue des Martyrs, 38054 Grenoble, France ABSTRACT In this paper, we present CVD (Chemical Vapor Deposition) growth and passivation of tungsten (W) and titanium nitride (TiN) nanocrystals (NCs) on silicon dioxide and silicon nitride for use as charge trapping layer in floating gate memory devices. NCs are deposited in an 8 inches industrial CVD Centura tool. W and TiN are chosen for being compatible with MOSFET memory fabrication process. For protecting NCs from oxidation, a silicon shell is selectively deposited on them. Moreover, for a better passivation, TiN NCs are encapsulated in silicon nitride (Si3N4) in order to get rid of oxidation issues. After high temperature annealing (1050°C under N2 during 1 minute) XPS measurements point out that NCs are still metallic, which makes them good candidates for being used as charge trapping layer in floating gate memories.
INTRODUCTION Thanks to their discrete nature and intrinsic robustness towards defects in the surrounding dielectrics, Silicon nanocrystal (Si-nc) trapping layers offer several advantages on standard polySi floating gates, as improved data retention after endurance in particular at high temperatures1,2. It has also been shown that coupling the Si-nc concept with high-k control dielectrics, by improving the gate coupling ratio, enables Fowler-Nordheim (FN) program/erase, thus opening the paths for NAND Flash application3. However, one of the key limitations of Si-nc memories is the limited memory window which is not suitable for multi-level memory applications. Metal nanocrystals are candidates to increase the number of charges stored (larger density of states and larger work function). One way to obtain a dense array of metal nanocrystals is to evaporate and a thin metal layer followed by a rapid thermal annealing4,5. However, in the frame of 3D integration, a conformal depositon of microelectronics metal nanocrystals is necessary. In this paper, we present the CVD growth of tungsten and titanium nitride nanocrystals. Passivation of these nanocrystals by a silicon shell is also presented. EXPERIMENT Nanocrystals growth and passivation are done in an 8 inches industrial CVD Centura tool. All fabrication steps are made in different chamber but in the same equipment during the same run. XPS measurements were performed on a customized Thermo Electron Theta 300 spectrometer, directly interfaced to the Alcatel vacuum carrier pod via a vacuum transfer chamber (10 mbar range). All measurements were performed on full 200 mm wafers without any cut. A Hitachi MEB5000 scanning electron microscope (SEM) is used for nanocrystals observation. High
resolution transmission electron microscope (HRTEM) analysis are performed to confirm cry
