Design of Efficient Ternary Operators for Scrambling in CNTFET Technology
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RESEARCH ARTICLE-ELECTRICAL ENGINEERING
Design of Efficient Ternary Operators for Scrambling in CNTFET Technology Laxmi Kumre1 · Trapti Sharma1 Received: 17 December 2019 / Accepted: 29 May 2020 © King Fahd University of Petroleum & Minerals 2020
Abstract Digital computation using ternary logic allows compact and energy-efficient digital design due to the reduction in circuit interconnects and chip area. CNFET unique characteristic of scalable threshold voltage value by utilizing the CNTs of different chirality vectors makes it a suitable option to realize ternary logic designs. This work presents hardware-efficient and low-power ternary operators exclusively used for scrambling applications in crypto-algorithms. The proffered designs are based on multiplexing the output digits among various unary cycle operators as the input trits. Extensive HSPICE simulations are conducted using standard 32-nm CNFET Stanford model to calculate the performance parameters of the proposed circuits. The presented designs show a significant improvement in terms of average power consumption, component count and energy consumption as compared to earlier counterparts. Results for various proposed scrambling operators Sop3, Sop4 and Sop5 show about an average reduction in energy consumption of 80% as compared to previously presented scrambling operators. Moreover, the Monte Carlo simulation results reveal that the proposed designs are robust against the mismatches in the diameter of CNTs. Keywords Multi-valued design · Ternary logic · Scrambling operators · Crypto-algorithms · Carbon nanotube field effect transistor (CNFET) · Nanotechnology
1 Introduction Information security is a pivotal issue in a wireless communication system that is vulnerable to many security threats. Therefore, protecting the confidentiality, integrity and authenticity of transmitting data from unauthorized access is essential in various applications. Data scrambling is the process of confounding the data against unauthorized access, while data is traversing from the transmitter to the receiver in a digital communication system [1]. The prime motive of the scrambler is to encode the digital data on the transmitter side and decode it reversibly at the receiver side using de-scrambler without any loss in the information content [2].
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Trapti Sharma [email protected] Laxmi Kumre [email protected]
1
Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal, India
Digital computation using binary logic poses a serious challenge because the area covered by wire routing has increased to a greater extent as compared to the area occupied by active elements. As a result, more than 70% of on-chip capacitance is caused due to the presence of on-chip interconnects [3]. This interconnect causes coupling effects, produces a lot of energy and further increases the response time of the circuit. Thus, to resolve these problems, multi-valued logic (MVL) provides a suitable alternative that helps to work on m
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