Effects of Process Conditions on the Performance of Large Grain Poly-Silicon on Insulator (LPSOI) MOSFET for Advanced CM
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Effects of Process Conditions on the Performance of Large Grain Poly-Silicon On Insulator (LPSOI) MOSFET for Advanced CMOS Applications S. Shivani, K. L. Ng, C. F. Cheng, M. C. Poon, and Mansun Chan Department of Electrical and Electronic Engineering, Hong Kong University of Science & Technology, Sai Kung, Hong Kong ABSTRACT Effects of process annealing temperature on Metal-Induced-Lateral-Crystallization (MILC) growth rate and quality of MILC polysilicon formed were studied. Raman spectrum analysis was employed for material characterization. MILC polysilicon layer, which was formed by applying an optimum annealing condition together with post high temperature annealing, could be used to fabricate Thin-Film-Transistor (TFT) with considerably electrical improvements. This reflected that good quality of the polysilicon layer. It is believed that the proposed MILC formation method can be empolyed to produce large grain polysilicon on insulator (LPSOI) for advanced devices and circuits’ fabrication.
INTRODUCTION With increasing demand for higher packing densities of Very Large-Scale Integrated (VLSI) circuits, there has been much attention to Silicon-On-Insulator (SOI) devices. SOI devices possess considerable advantages of high packing density, easy isolation, simple process as well as the possibility to be used in 3-D integration. With the size of devices enters submicron region, the demand of higher integration is more aggressive than any practical scaling of conventional devices in the future. In order to achieve giga-scale integration and beyond, fabrication of devices in multiple levels is necessary. However, the production of SOI devices is an expensive process limited by equipment cost, throughput, and yield. TFT formed by polysilicon has similar structure as SOI, and it has been used in the load element in Static Random Access Memory (SRAM). Comparing TFT and SOI transistors, TFT is easier to fabricate in terms of starting material and compatibility with bulk process. However, its performance is usually very poor for high performance circuits because of small size of grain and presence of grain boundaries and intra-grain defects. Therefore, it is highly desirable to have large area polysilicon film with silicon grains having large size, high material quality, good uniformity and good controllability in order to improve the performance of the devices. This only requires a well-established silicon process. To achieve maximum flexibility make available from SOI technology, a method to form high quality silicon film on oxide and other insulating substrate is required [1]. We have previously demonstrated that with the combination of MILC and high temperature annealing on amorphous film, very large grain can be achieved [2, 3]. Despite the advantage of getting large grain by using MILC technology, there are some drawbacks. The first drawback is long time annealing used for conventional MILC varied from 50 to 90 hours at 500 °C to 550 °C. Also, the quality of the polysilicon formed is not very good and the grain size
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