Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors
This paper presents an innovative approach for the generation of test programs detecting path-delay faults in microprocessors. The proposed method takes advantage of the multiobjective implementation of a previously devised evolutionary algorithm and expl
- PDF / 318,047 Bytes
- 11 Pages / 430 x 660 pts Page_size
- 77 Downloads / 165 Views
Politecnico di Torino – Dipartimento di Automatica e Informatica - Torino, Italy {paolo.bernardi,michelangelo.grosso,edgar.sanchez, matteo.sonzareorda}@polito.it 2 University of Cyprus – Department of Electrical and Computer Engineering - Nicosia, Cyprus {christou,mmichael}@ucy.ac.cy
Abstract. This paper presents an innovative approach for the generation of test programs detecting path-delay faults in microprocessors. The proposed method takes advantage of the multiobjective implementation of a previously devised evolutionary algorithm and exploits both gate- and RT-level descriptions of the processor: the former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is used for the automatic generation of test programs able to excite and propagate fault effects, based on a fast RTL simulation. Experiments on an 8-bit microcontroller show that the proposed method is able to generate suitable test programs more efficiently compared to existing approaches. Keywords: MOEA, path-delay testing, microprocessor, BDD.
1 Introduction In order to guarantee product quality for today’s microprocessor cores, traditional stuck-at tests are no longer sufficient and more complex fault models have to be considered when devising test strategies. At-speed delay fault testing, in particular, has been widely addressed by academia and is becoming common practice in industry [1]-[4]. Among all existing delay fault models, the path-delay fault model is considered the most accurate since it can detect both lumped and distributed delays [3][5], but also the most challenging, due to the enormous number of faults (paths). Delay test has been approached adopting different strategies, purely relying on an external tester or applying structural self-testing methodologies such as Built-In SelfTest (BIST), or exploiting the execution of suitable self-test programs. The latter strategy is usually referred to as Software-Based Self-Test (SBST) and is generally more affordable, as it exploits the processor instructions in the normal mode of operation; it can be used in stand-alone modules as well as when the processors are deeply embedded in a System on Chip (SoC) and their accessibility is reduced. Regarding test generation addressing path-delay faults, several techniques exist for enhanced full-scan circuits, based on either structural ATPG tools [6][7] or functionbased tools using Binary Decision Diagrams (BDDs) [8]-[10] and Boolean-SAT M. Giacobini et al. (Eds.): EvoWorkshops 2008, LNCS 4974, pp. 224–234, 2008. © Springer-Verlag Berlin Heidelberg 2008
Exploiting MOEA to Automatically Generate Test Programs for Path-Delay Faults
225
[11][12] implementations. Some work on software-based test generation has been done exploiting deterministic techniques [13]-[15]. Evolutionary algorithms have been successfully exploited for the automatic generation of program sets for verification, test [16], and diagnosis [17] for processors described at different levels of abstraction. In most cases, the evolution
Data Loading...
