High Gain, Silicon-on-insulator Photodetector with Multiple Gates and a Nanowire Based Narrow-wide-narrow Channel
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High Gain, Silicon-on-insulator Photodetector with Multiple Gates and a Nanowire Based Narrow-wide-narrow Channel Anita Fadavi Roudsari1, Simarjeet S. Saini1, Nixon O2, and M. P. Anantram3 1 Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Ontario, Canada N2L 3G1 2 DALSA Corporation, Waterloo, Ontario, Canada N2V 2E9 3 Electrical Engineering Department, University of Washington, Seattle, WA 98195-352500 U.S.A ABSTRACT We propose a phototransistor geometry that incorporates silicon nanowires (SiNW) in the device channel. A set of two gates controls the charge flow inside the NW. This improves the device photo-response more than 10x when compared with a single gate phototransistor, leading to a photo-responsivity of greater than 104(A/W), while the dark properties of both devices are similar. INTRODUCTION One-dimensional (1D) structures such as carbon nanotubes (CNT) and silicon nanowires are being widely investigated in fabricating the future generation of sensors for light and biomolecules. The small size of nano-structures lowers the power consumption in the device; it is also possible to fabricate arrays of independently operating devices to speed up the operation of the whole system for real time applications [1]. Other unique features of 1D structures such as quantum mechanical effects, improved electrostatic control and good transport characteristic along their length have also proved useful in bio- applications [2-4], as well as optical switches and photodetectors [5-6]. The poor optical absorption of individual nanowires (NW) in a photodetector is usually compensated by integrating them into gain producing structures such as photoconductors and phototransistors [6-8]. Silicon NW-based phototransistors are also being studied for imaging applications, due to their fabrication compatibility with CMOS technology [7], [9]. This work is devoted to investigating the role of electrostatics in NW based, Silicon on Insulator, Metal Oxide Semiconductor (SOI MOS) phototransistors. The NW is integrated in device channel, where its small diameter improves the gate control over the potential barrier and the charge flow. In the next step, in order to benefit from this property we add a secondary gate to the device and change the channel geometry. The photocurrent of the new structure is increased and photo-responsivities of greater than 104 A/W are achieved. THEORY Figure 1 shows a three dimensional SOI MOS phototransistor. The 200nm thick active region, including n+ source and drain areas and a p-type channel (doping: 1016cm-3), is located on top of a 200nm thick buried SiO2. The polysilicon gate (work-function: 4.17eV) is separated
from the channel by a 20nm oxide. The channel under the gate oxide is 500nm wide and 1µm long. x y
Gate Gate Oxide
z
Source
Channel
Drain
Buried Oxide
Figure 1. SOI MOS photodetector; W = 500nm, L = 1µm, gate oxide thickness = 20nm, Si and buried oxide thickness = 200nm. Active region is surrounded by SiO2 on both sides. The device is biased under latera
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