Impact of Single-Event Upsets in Deep-Submicron Silicon Technology
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Impact of Single-
Event Upsets in Deep-Submicron Silicon Technology Robert Baumann
Abstract The once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliabilityfailure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed. Keywords: radiation, semiconductors, single-event upsets, soft errors.
Introduction As the dimensions and operating voltages of the electronics we increasingly depend upon are reduced to satisfy the ever-increasing demand for higher density (functionality) and lower power (portability), their sensitivity to radiation increases dramatically. In normal terrestrial applications, the predominant radiation issue is the single-event upset (SEU). This is a broad term applying to situations where a single radiation event (as opposed to dose effects, where long-term radiation exposure degrades device parameters over time) causes a circuit or device to malfunction either temporarily (soft error or soft single-event latch-up) or permanently (single-event burnout, hard single-event latch-up, and single-event gate rupture). Since the “hard” single-event failures are extremely rare in the terrestrial environment, it is reasonable to limit our focus to “soft errors” in advanced silicon technology. In the last two decades, three key radiation mechanisms have been demonstrated to cause soft errors in semiconductor devices at terrestrial altitudes. In the late
MRS BULLETIN/FEBRUARY 2003
1970s, alpha particles in packaging materials were shown to be the dominant cause of SEU in dynamic random-access memory (DRAM) devices.1 During the same era, high-energy (1 MeV) neutrons from cosmic radiation were shown to cause soft errors in different types of semiconductor devices,2 and in the mid-1990s, highenergy cosmic radiation was shown to be the dominant source of soft errors in DRAM devices.3–5 Concurrently, a third mechanism was identified6 —soft errors from low-energy cosmic neutron interactions with 10B in integrated-circuit (IC) materials, specifically in borophosphosilicate glass (BPSG) used as insulator layers in IC manufacturing. This mechanism has recently been shown to be the dominant source of soft errors in 0.25-µm and 0.18-µm (effective channel length of the minimum size transistor) static random-access memories (SRAMs) fabricated with BPSG.7,8 To better appreciate how soft errors are generated at the device level, it is instructive to consider the re
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