Incorporation of Nitrogen Atoms at Si/SiO 2 Interfaces of Field Effect Transistors (FETs) to Improve Device Reliability
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explained in this paper in the context of a microscopic model for the creation of anomalous positive charge (APC) centers at Si-SiO 2 interfaces [11]. PREPARATION OF NITRIDED Si-Si0
2
INTERFACES FOR FETs
Fabrication of the Si-SiO2 structures has been separated into three independently controlled process steps [12,13]: i) Si-Si02 interface formation by plasma-assisted oxidation/nitridation at 300°C; ii) deposition of Si02 by remote PECVD at 300'C; and iii) chemical and/or structural relaxation of Si-Si02 interfaces and oxide films by rapid thermal annealing at 900'C, or equivalent thermal exposures during downstream processing. These steps were used in the fabrication of two device structures: i) metal-oxide-semiconductor (MOS) capacitors with Al-gate electrodes, and ii) field effect transistors (FETs) with phosphorus doped polycrystalline-silicon gate electrodes. For the MOS capacitors, the substrates were p/p+ Si (100) wafers with an epi-layer resistivity of -10 f0-cm; lower resistivity wafers with a hole concentration of p-4xl01 7 cm"3 were used for the FETs. For the MOS capacitors: after a standard, high temperature, RCA clean followed by an HFrinse, the substrates were inserted into a multichamber, UHV-compatible plasma processing system and subjected to a 300TC remote plasma-assisted oxidation in which the 0 source gas was 02, N20, or an N20/02 mixture. This process formed the Si-Si02 interface as well as 0.5-0.6 nm of Si02 that acted as a template for the SiO2 deposition that followed. The rf power at 13.56 MHz was 15 W, the process pressure was 300 mTorr, and 02, N20 or N20/02 mixtures at flow rates between 10 and 20 sccm were co-excited with He at a flow rate 200 sccm. Following the plasmaassisted oxidation, 15 nm of SiO2 was deposited by remote PECVD at a pressure of 300 mTorr and a temperature of 300'C. A He/N20 mixture (200 sccm/20 sccm) was excited in a 15 W rf plasma upstream from the Si wafer and 2 sccm of 10% SiH4 in He was introduced downstream through a dispersal ring. MOS capacitors were fabricated using Al-gate electrodes patterned by standard photolithographic techniques. The maximum processing temperature for the MOS capacitors was 400'C, the temperature of the PMA following the Al-gate electrode processing. The Si-Si02 interfaces incorporated into the FETs were formed in essentially the same manner as the MOS capacitors by oxidation in different N20/02 mixtures. However, there were two differences in the process. The Si surface for the gate oxide was not subjected to a pre-oxidation RCA clean, but instead, a field oxide about 200 nm thick was grown on the entire wafer, and the gate oxide region was defined by a combination of low-pH and dilute HF oxide etching. This results in smoother interfaces for Si (100) than an RCA clean, and hence yields a reduced fall-off of the channel mobility as a function of the electric field at the Si surface [14]. Second, the oxide layers for the FETs, typically 5.5-6.0 nm in thickness, were deposited by remote PECVD using both 02 and N20 as the O-atom sourc
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