Investigation on the Work Function of Tungsten and Thermal stability of W/SiO 2 /Si, W/SiON/Si and W/HfO 2 /Si Gate Stac
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0917-E12-01
Investigation on the Work Function of Tungsten and Thermal stability of W/SiO2/Si, W/SiON/Si and W/HfO2/Si Gate Stacks Pei-Chuen Jiang1, Jen-Sue Chen2, K. H. Cheng3, T. J. Hu3, K. B. Huang3, and F. S. Lee3 1 Department of Materials Science and Engineering, National Cheng Kung University, No.1, Ta-Hsueh Road, Tainan, 701, Taiwan 2 National Cheng Kung University, Tainan, 701, Taiwan 3 Taiwan Semiconductor Manufacturing Company, Tainan, Taiwan ABSTRACT Replacement of poly-Si and SiO2 with new gate electrode and high k gate oxide is an inevitable trend for next-generation CMOS integrated circuits. Therefore, work function (Φm) of gate electrodes as well as the thermal stability and electrical behaviors of MOS capacitors should be understood. In this study, tungsten (W) is applied as the gate electrode and the gate dielectric materials are SiO2, SiON and HfO2. Φm of W and electrical properties of the MOS structures are investigated. Φm,measured of W is calculated from the flat-band voltage (VFB) of MOS capacitors with dielectrics of various thicknesse. For W/SiO2/Si structure, the Φm,measured of W is 4.67 V; however, the Φm,measured of W in W/SiON/Si and W/HfO2/Si structures is 4.60 V and 4.84 V, respectively. The result means that the Φm,measured of W in W/HfO2/Si structures has extrinsic contributions to Fermi level pinning. The phase of as-deposited W is β-W (or β-W+α-W) phase and transfers to α-W+WO3 mix phase after annealing at 500oC in N2+H2 ambient for 30 min. The trapped charges and oxide charges of dielectric are reduced after annealing. However, the EOT of W/SiO2/Si increases significantly after annealing, indicating the thermal stability of this capacitor is poor.
INTRODUCTION Poly-Si/SiO2 stacks have been utilized as the gate structure of MOSFETs (metal-oxide-semiconductor field-effect transistors) for decades. However, the high direct tunneling current precludes the use of SiO2 as gate dielectrics when its thickness decreases to below 2 nm in the sub-100nm generation. In addition, the conventional poly-silicon gate electrode of CMOS devices suffers several problems, such as gate depletion and boron penetration into the channel region [1-4]. In order to solve this problem, high dielectric constant (high k) materials and metallic materials are employed as gate dielectric and gate electrode, respectively. Accompanied by the exploration of high k gate oxides, researchers have also paid attention to find new materials for gate electrodes. The key parameters for new gate electrode materials included work function, resistivity and compatibility with the existing semiconductor processes. However, work function of metal gate electrodes would be modulated by Fermi level pinning effect of gate dielectrics [5-7]. When a semiconductor or a dielectric comes into contact with a metal, the wave functions of the two sides interact and new wave functions are formed in the immediate neighborhood of the interface [8]. Charging of these interface states creates a dipole that tends to drive the band lineup toward a
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