Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing System
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Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems Nacer-Eddine Zergainoh,1 Ludovic Tambour,1, 2, 3 Pascal Urard,2 and Ahmed Amine Jerraya1 1 TIMA
Laboratory, National Polytechnique Institute of Grenoble, 46 Avenue F´elix Viallet, 38031 Grenoble Cedex 1, France Microelectronics, 850 Rue Jean Monnet, 38926 Crolles Cedex, France 3 CIRAD, TA 40/01, avenue Agropolis Lavalette, 34398 Montpellier Cedex 5, France 2 ST
Received 3 October 2004; Revised 14 April 2005; Accepted 25 May 2005 We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time. Copyright © 2006 Hindawi Publishing Corporation. All rights reserved.
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INTRODUCTION
As the complexity of the high-throughput dedicated digital signal processing (DSP) systems under hardware design increases, development efforts increase dramatically. At the same time, the market dynamics for electronic systems push for shorter and shorter development times [1]. In order to meet the design time requirements, a design methodology for VLSI dedicated DSP system that favors reuse and early error detection is essential. One idea, largely widespread and applied to design DSP systems, is to adopt a modular approach based on divide-and-conquer strategy (recursive). The global complexity of the system should be divided into subsystems (i.e., elementary signal processing functions), well known and of easily accessible complexity such as filter (FIR, IIR), fast Fourier transform (FFT), Viterbi decoder, and so forth. The system can be obtained by the hierarchical assembly of these common functions of signal processing (also known as IP blocks). The intellectual-property- (IP)based design is obviously an important issue for improving not only design productivity, but also design from the higherlevel abstraction [2, 3]. However, designers encounter two major problems with the IP-block-based design approach [2–4]. The first problem is the difficulty in using IPs blocks for high-throughput DSP systems that require various performances (throughput) or
functions with nonstandard algorithms [5]. This is because VLSI DSP system cannot be parameterized for global performance and functions; for example, necessary processing cycles cannot be adjusted for IPs blocks. The second problem comes from interfacing of IPs blocks between themselves. Designers have to design IPs blocks that can c
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