Manipulation of Germanium Nanocrystals in a Tri-Layer Insulator Structure of a Metal-Insulator-Semiconductor Memory Devi
- PDF / 554,874 Bytes
- 6 Pages / 595 x 842 pts (A4) Page_size
- 71 Downloads / 167 Views
MANIPULATION OF GERMANIUM NANOCRYSTALS IN A TRI-LAYER INSULATOR STRUCTURE OF A METAL-INSULATOR-SEMICONDUCTOR MEMORY DEVICE L.W. Teo,1 C.L. Heng,1 V. Ho,2 M. Tay,2 W.K. Choi,1,2 W.K. Chim,1,2 D.A. Antoniadis,1,3 E.A. Fitzgerald1,3 1 Singapore-MIT Alliance, Advanced Materials for Micro and Nano Systems Programme, National University of Singapore 2 Department of Electrical & Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576 3 Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA ABSTRACT A metal-insulator-semiconductor (MIS) device that consists of germanium (Ge) nanocrystals embedded in a novel tri-layer insulator structure is proposed for memory applications [1]. The tri-layer structure comprises a thin (≈5nm) rapid thermal oxidation (RTO) silicon dioxide (SiO2) layer, a Ge+SiO2 middle layer (6 - 20 nm) deposited by RF co-sputtering technique and a RF-sputtered silicon dioxide capping layer. High-resolution transmission electron microscopy (HRTEM) results show that Ge nanocrystals of sizes ranging from 6 – 20 nm were found after rapid thermal annealing of the trilayer structure at 1000oC for 300s. The electrical properties of these devices have been characterized using capacitance versus voltage (C-V) measurements. A significant hysteresis was observed in the C-V curves of these devices, indicating charge trapping in the composite insulator. Comparison with devices having similar tri-layer insulator structure, but with a pure sputtered oxide middle layer (i.e. minus the Ge nanocrystals), clearly indicated that the observed charge trapping is due to the presence of the Ge nanocrystals in the middle layer. The C-V measurements of devices without the capping SiO2 layer exhibited no significant hysteresis as compared to the embedded Ge nanocrystal tri-layer devices. The HRTEM micrographs showed that the presence of the capping oxide is critical in the formation of nanocrystals for this structure. By varying the thickness of the middle layer, it was found that the maximum nanocrystal size correlates well with the middle layer thickness. This indicates that the nanocrystals are well confined by the RTO oxide layer and the capping oxide layer. In addition, Ge nanocrystals formed using a thinner middle layer were found to be relatively uniform in size and distribution. This structure, therefore, offers a possibility of fabricating memory devices with controllable Ge nanocrystals size. INTRODUCTION Self-assembled silicon nanocrystals, which utilize Coulomb blockade effect, have been used to fabricate memory devices [2,3]. By using these electrically isolated charge-storage dots, the amount of charge leakage through localized oxide defects can be greatly reduced [4]. As a result, a thinner tunneling oxide layer, which enables faster write and erasing speeds, can be used as compared to conventional flash memory cells which require a relative thick tunneling oxide to achieve good data retention performance. The advantages of replacing the conventional floating ga
Data Loading...
