Model-Order Reduction of High-Speed Interconnects Using Integrated Congruence Transform
With the rapid developments in Very Large Scale Integration (VLSI) technology at both the chip and package level, the operating frequencies are quickly reaching the vicinity of GHz and switching times are getting to the sub-nano second levels. The ever in
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School of Information Technology and Engineering (SITE), Univ. of Ottawa, Ottawa, ON, Canada, K1N 6N5 [email protected]. Dept. of Electronics, Carleton Univ., Ottawa, ON, Canada, K1S 5B6 {msn,achar}@doe.carleton.ca
1 High-Speed Interconnects and Its Effects on Signal Propagation With the rapid developments in Very Large Scale Integration (VLSI) technology at both the chip and package level, the operating frequencies are quickly reaching the vicinity of GHz and switching times are getting to the sub-nano second levels. The ever increasing quest for high-speed applications has placed higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections and crosstalk. As depicted by Figure 1, interconnects can exist at various levels of design hierarchy such as on-chip, packaging structures, multichip modules, printed circuit boards and backplanes. In addition, the trend in the VLSI industry towards miniature designs, low power consumption and increased integration of analog circuits with digital blocks has further complicated the issue of signal integrity analysis. It is predicted that interconnects will be responsible for majority of signal degradation in high-speed systems [1]. High-speed interconnect problems are not always handled appropriately by the conventional circuit simulators, such as SPICE [2]. If not considered during the design stage, these interconnect effects can cause logic glitches which render a fabricated digital circuit inoperable, or they can distort an analog signal such that it fails to meet specifications. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in high-speed designs. Hence it becomes extremely important for designers to simulate the entire design along with interconnect subcircuits as efficiently as possible while retaining the accuracy of simulation. Speaking on a broader perspective, a “high-speed interconnect” is the one in which the time taken by the propagating signal to travel between its end points can not be neglected. An obvious factor which influences this definition is the physical extent of the interconnect, where the longer the interconnect, the more time the signal takes to travel between its end points. Smoothness of signal propagation suffers once the line becomes long enough for signals rise/fall times to roughly match its propagation time through the line. Then the interconnect electrically isolates the
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Fig. 1. Electrical interconnects are encountered at all levels of design hierarchy.
driver from the receivers, which no longer function directly as loads to the driver. Instead, within the time of signals transition between its high and low voltage levels, the impedance of interconnect becomes the load for the driver and also the input impedance to the receivers [1]. This leads to various transmission line effects, such as reflections, overshoot, undershoot, cr
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