Modeling and Simulation of Parasitic Effects in Stacked Silicon
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0970-Y02-02
Modeling and Simulation of Parasitic Effects in Stacked Silicon Gunter Elst Design Automation, Fraunhofer IIS, Zeunerstrasse 38, Dresden, 01069, Germany
Abstract Devices and interconnect structures of new semiconductor and packaging technologies show parasitic physical effects with a growing influences of the system behavior. Therefore, the design technology has to be developed and adjusted to ensure high system performance and reliability of these very complex systems on chip and in a stack. The influences of parasitic effects on the circuit behavior have to be minimized within the design process. Typical parasitic effects of the Vertical System Integration (VSI®) by stacked silicon are discussed in this paper. Effects like electro thermal coupling, electromagnetic interactions, and the sensitivity due to parameter variations and their influence to the system behavior are identified and modeled. Approaches for minimization of these influences by design modifications are presented. Keywords stacked silicon, 3D integration, vertical system integration, design for manufacturability, robust design, modeling 1 INTRODUCTION Due to the potential of new integration technologies the economical realization of highly complex and intelligent systems will be possible for many applications. These capabilities will be as driver for worldwide trends, as “Smart Devices”, “Autonomous Intelligent Systems”, “Ambient Intelligence”, or “Reconfigurable Computing”. Therefore, the ITRS roadmap also predicts an increasing demand for systems-onchip (SoC) and systems-in-package (SiP) respectively. The Vertical System Integration (VSI®) in silicon is one
of the most important future technologies for manufacturing of such very complex chip systems. Not only the manufacturing technology has to be developed but also the design technology has to be tailored for requirements concerning high system performance and reliability. There are physical effects with a growing influence on the circuit behavior. The VSI with freely positioned inter-chip-vias is characterized by a very high density of inter-chip wiring and active devices. Because of these characteristics some physical effects will play an increasing role related to the device function, especially concerning cross talk and interconnect delays. Another problem caused by power dissipation and the high density of active devices is thermal management. Furthermore, testing of the very complex stacked systems is crucial task. The influence of technology features to circuit behavior has to be minimized within the design process. This requires new design rules, models, methodologies, and tools for CAD of electronic systems implemented using VSI technologies. New methods will ensure the design ability, higher design efficiency and better design quality and lead to a higher system performance, robustness and reliability. This paper discusses the parasitic effects of VSI systems, design strategies relating to testability and power dissipation, and shows approaches for design for manufactura
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