Molecular-Beam Epitaxy and Device Applications of III-V Semiconductor Nanowires
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antum mechanics, by utilizing artificial structures such as quantum wells, wires, and dots. In these structures, new physical effects appear, such as the formation of new quantum states in Single and coupled quantum structures, artificial miniband formation in superlattices, t u n n e l i n g and resonant t u n n e l i n g in Single and multiple barriers, propagation of phase-coherent guided electron waves in quantum wires, conductance oscillations in small tunnel junctions due to single-electron tunneling, and so on. We expect that these effects will offer rieh functionality in next-generation semiconductor quantum ULSls based on artificial quantum structures, with fea ture sizes in the ränge of one to a few t e n s of n a n o m e t e r s . Beyond t h i s , molecular-level ULSls using exotic materials and various chemical and electrochemical processes other than the Standard semiconductor ones may appear, butat present, they still seem to be too far in the future for realistic consideration for industrial applications. One of the important building blocks for future quantum ULSls is the type of wire structures discussed in this special
issue. Nanowires may be made out of semiconductors, metals, or other materials. We describe in this article the formation, properties, and device appli cations of two types of lll-V Compound semiconductor nanowires which have been grown by molecular-beam-epitaxyb a s e d (MBE-based) t e c h n i q u e s at Hokkaido University's Research Center for Interface Q u a n t u m Electronics (RC1QE). Since we are forming these wires as building blocks for quantum devices, some emphasis is placed here on the de vice applications of the wires.
Methods for Semiconductor Wire Formation Approaches for the formation of semi conductor wires include the following: 1. wire fabrication by directly applying Standard Si ULSI processing technologies, such as electron-beam (EB) lithography, dry etching, and oxidation of Silicon or silicon-on-insulator (SOI) wafers; 2. wire formation on lll-V multilayer heteroepitaxial wafers by EB lithography and etching; 3. selective depletion of a two-dimensional electron gas (2DEG) in lll-V multilayer heteroepitaxial wafers by a special Schottky gate that has a split portion under which a wire is formed, as shown in Figure la; 1 4. formation of lll-V semiconductor wire structures by selective growth on specially p a t t e r n e d Substrates, which is sometimes referred to as substrateencoded size-reducing epitaxy (SESRE);2,3 5. formation of lll-V semiconductor wire structures by selective-area growth us ing patterned insulator Windows;4 and 6. direct fabrication of nanostruetures by scanning probe-induced atom manipulation or surface reaction.5 Among these, Approach 1 is the most practical, but process-induced damage can be a serious problem in Si ULSI dry processes. Additionally, achievable sizes, size uniformity, size controllability, and interface smoothness are also not quite satisfactory. Thus either drastic improvements in nanofabrication or the exploitation
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