Multi-Objective-Based Approach to Optimize the Analog Electrical Behavior of GSDG MOSFET: Application to Nanoscale Circu
In this chapter, the small signal parameters behavior of Gate Stack Double Gate (GSDG) MOSFET are studied and optimized using multi-objective genetic algorithms (MOGAs) for nanoscale CMOS analog circuits’ applications. The transconductance and the OFF-cur
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Abstract In this chapter, the small signal parameters behavior of Gate Stack Double Gate (GSDG) MOSFET are studied and optimized using multi-objective genetic algorithms (MOGAs) for nanoscale CMOS analog circuits’ applications. The transconductance and the OFF-current are the small signal parameters which have been determined by the analytical explicit expressions in saturation and subthreshold regions. According to the analytical models, the objectives functions, which are the pre-requisite of genetic algorithms, are formulated to search the optimal small signal parameters in order to obtain the best electrical and dimensional transistor parameters to obtain and explore the better transistor performances for analog CMOS-based circuit applications. Thus, the encouraging obtained results may be of interest to practical applications. The optimized design is incorporated into circuit simulator to study and show the impact of our approach on the nanoscale CMOS-based circuits design. In this context, we proposed to study the electrical behavior of a ring oscillator circuit. In this study a great improvement of the oscillation frequency has been recorded in our case. The main advantages of the proposed approach are its simplicity of implementation and provide to designer optimal solutions that suites best analog application. Keywords Analog application · CMOS · Double gate algorithm · MOGA · Small signal · Submicron
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T. Bendib (B) · F. Djeffal LEA, Department of Electronics, University of Batna, 05000 Batna, Algeria e-mail: [email protected]; [email protected] F. Djeffal e-mail: [email protected]; [email protected] G.-C. Yang et al. (eds.), IAENG Transactions on Engineering Technologies, Lecture Notes in Electrical Engineering 229, DOI: 10.1007/978-94-007-6190-2_24, © Springer Science+Business Media Dordrecht 2013
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Fig. 1 Cross-sectional view of the conventional MOSFET
1 Introduction Because the widely uses of the silicon based devices in many fields of physics, a lot of aspects related to the behavior of CMOS devices, and a global understanding of their effect structure and properties became increasingly important due to the reduction in chip sizes and to the increase of the operation speed [1]. The downscaling of device dimensions has been the primary factor leading to improvements in Integrated Circuits (CIs) performance and cost, which contributes to the rapid growth of the semiconductor industry. As MOSFET gate length (Fig. 1) enters nanoscale field, small signal parameters and short channel effect such as off current, threshold voltage roll-off and draininduced-barrier-lowering become increasingly significant, which limit the scaling capability of MOSFET design [2, 3]. Downscaling MOSFETs to their limits is a key challenge faced by the nanoelectronic industry. Therefore, a new designs and structures become necessary to overcome these challenges. Double-Gate (DG) MOSFETs have
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