Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction
- PDF / 3,093,046 Bytes
- 12 Pages / 595.276 x 790.866 pts Page_size
- 120 Downloads / 157 Views
Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction P. Meenakshi Vidya1 • S. Sudha1 Received: 17 April 2020 / Revised: 17 April 2020 / Accepted: 30 May 2020 Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced by the use of a high resolution digital-to-time converter with its range and duty cycle calibration in background. Also, the nonlinearity of the analog front-end circuit in the proposed hearing aid SoC is reduced by introducing a switching block based dynamic element matching process. Furthermore, an improved noise reduction algorithm is proposed based on pitch based voice activity detector and multiband complex spectral subtraction to improve the performance of the proposed hearing Aid SoC. The proposed hearing aid SoC is designed in an 180 nm CMOS technology. The simulation results show that, integrated jitter of the proposed structure is reduced to 0.9 psrms and it achieves a signal to noise ratio of 89.24 dB. The total power consumption of this hearing aid is only 996 lW for 1.2 V supply that shows the superiority of the proposed work than existing works. Keywords Hearing aid SoC Analog front-end (AFE) Fractional dividers (FDIV) DSP platform Noise reduction (NR)
1 Introduction The main components of hearing aid SoC are analog frontend (AFE) circuit, digital signal processing (DSP) platform, and other analog and digital circuit modules. Furthermore, it includes several speech compensation and noise reduction algorithms [1–3]. The modern hearing aid SoC are difficult to design because it should provide a constant compromise between power, size and performance. Nowadays, this hearing aid devices includes number of additional features and there is a requirement of a smaller size device to make them invisible. Thus, the entire analog, digital, power supply and clock modules are integrated in a single chip. The DSP platform of hearing aid SoC includes an ASIP and numerous accelerators to provide flexible design. The conventional hearing aid SoC uses application-specific & P. Meenakshi Vidya [email protected] 1
ECE Department, Easwari Engineering College, Chennai 600089, India
integrated circuits (ASIC) to consume less power [4]. But, the algorithms on ASICs are difficult to modify and are requiring very high cost and long time. These issues can be solved with the help of a general purpose digital signal processor (GPDSP) platform. Even though the flexibility of this processor is good enough, it consumes more power. Hence, the complete usage of ASIC power efficiency can be achieved by an alternative choice namely, an applicati
Data Loading...
