Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory
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0961-O05-12
Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory Udayan Ganguly1, Tuo-Hung Hou2, and Edwin Chihchuan Kan3 1 ADC-FEP, Applied Materials, 974 E Arques Street B 81, Sunnyvale, CA, 94085 2 Electrical and Computer Engr, Cornell University, 323 Phillips Hall Cornell University, Ithaca, NY, 14853 3 Electrical and Computer Engr, Cornell University, 404 Phillips Hall Cornell University, Ithaca, NY, 14853
ABSTRACT Recently, metal nanocrystal (NC) based carbon nanotube (CNT) memory has been demonstrated with sub-5V low bias programming, single electron sensitivity, but poor roomtemperature retention. The process integration of an ultra-thin tunnel dielectric is essential for lateral, vertical scaling and reliable room-temperature operations. Low defect density and conformal deposition on the nanotube are required to enhance the performance as a tunnel barrier. Additionally, Au contamination in the CNT decreases the on/off current ratio in the CNTFETs by substantially increasing the off current. Consequently, the dielectric should function as a good diffusion barrier for Au in the nanocrystals. We have explored composite tunneling dielectric film with SiO2 seed layer for conformal high-k deposition to demonstrate minimal Au contamination and improved retention. Room temperature retention of better than three days has been observed. INTRODUCTION The one-transistor (1T) flash memory cell has been the present technology standard for nonvolatile memory applications [1]. As silicon-based flash memory scaling faces physical and fundamental limitations, various solutions are being proposed. Engineering the floating gate has been a major focus. Silicon nitride traps have replaced thin-film floating gate for charge storage to reduce the bit error from single global defect that causes short retention time error [2]. Selfassembled semiconductor nanocrystal floating gates have been alternately proposed to reduce the operating voltage by allowing more aggressive tunneling dielectric scaling [3, 4]. Further, metal nanocrystals have been implemented, which provide better electrostatic, higher density of states for faster tunneling, and choice of different work-functions for better retention [5-7]. A parallel direction of innovation has been engineering the channel. Nanowire based channels in conjunction with semiconductor nanocrystal based storage has been explored [8, 9]. Significant enhancements in density, retention and memory window have been indicated as the channel approached a one dimensional (1-D) nanowire [8]. The fabrication of 1-D channel by top-down approach involves special sub-lithographic fabrication, but can be easily realized with the help of bottom-up self-assembly. Single-wall carbon nanotubes (SWNT) channels have been used as prototypes. Trap-based storage has been demonstrated using a SWNT channel [10]. Recently we have demonstrated a SWNT memory with charge storage in metal nanocrystals self-aligned to
the SWNT [11]. The unique electrostatics of thi
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