Screen Printable Semiconductor Grade Inks for N and P type Doping of Polysilicon
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MRS Advances © 2016 Materials Research Society DOI: 10.1557/adv.2016.118
Screen Printable Semiconductor Grade Inks for N and P type Doping of Polysilicon Aditi Chandra1, Mao Takashima1, Martha Montague1, Joey Li1, Arvind Kamath1 1
ThinFilm Electronics, San Jose, CA, 95134 United States.
ABSTRACT This article describes the electrical and physical properties of polysilicon doped with novel N+ and P+ screen printed inks using a thermally activated process. Unique ink formulations for N and P type doping of silicon are evaluated in volume production in order to enable a low cost, high throughput process. Inks can be used with multiple substrate types and form factors. The concentrated doping source combined with thermal drive in and activation results in degenerately doped layers of polysilicon. Inks are semiconductor grade which is demonstrated by their use in fabricating high mobility, low leakage Thin Film Transistor (TFT) devices on 300 mm stainless steel substrates. Reproducible sheet resistance values (700 A polysilicon) can be engineered from levels typically ranging from 200 - 2000 ohm/sq. The additive approach substitutes the use of high capital cost ion implantation and lithography processes. The ink formulation results in screen printed widths capable of ranging from 100-300 um. As both N and P type layers can be printed adjacent to each other, it is critical to prevent cross doping using surface preparation techniques. Post doping cleaning of surfaces can be achieved in-situ or by plasma removal depending on process integration and product considerations. Reproducibility and uniformity data to demonstrate manufacturability in a production environment is shown. In summary, a simple, low cost, high throughput additive process based on proprietary inks that can be used in multiple product flows (CMOS TFT, Solar etc.) is demonstrated. INTRODUCTION Printed Electronics has received considerable attention in recent years 1-4. In particular, we have shown that high performance polysilicon TFT devices based on printable silicon ink and screen printed dopants on high temperature substrates is used to make low cost RF capable devices (with limited transistor count) in a production environment 5-7. A key enabling technology is the use of screen printed n and p type silicon dopants that completely eliminates expensive ion implantation equipment from the manufacturing flow. This results in a low maintenance, high throughput, and low step count process integration module. This approach can also be used for other technologies (such as c-silicon based solar) where manufacturing simplicity may be the primary objective rather than device density. Several printed materials that can act as sources for thermal diffusion and activation of n and p dopants in silicon have recently received attention 8-10. This work examines custom materials that can meet stringent integration and device requirements for CMOS TFT technology. This includes a) semiconductor grade purity (to meet device lifetime and leakage requirements) b) tight do
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