Self-Aligned Solution-Processed Zinc-Tin Oxide Thin-Film Transistors with High-K Solution-Processed Gate Dielectric
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Self-Aligned Solution-Processed Zinc-Tin Oxide Thin-Film Transistors with High-K Solution-Processed Gate Dielectric Chen-Guan Lee1, Soumya Dutta1 and Ananth Dodabalapur1 1 Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758, USA ABSTRACT We demonstrate high performance zinc-tin oxide (ZTO) thin-film transistors (TFTs) with low operation voltage, small channel length and low parasitic capacitance. Both the zinc tin oxide and the high-k dielectric, ZrO2, were solution processed by sol-gel methods. A self-aligned process was employed to minimize the parasitic capacitance. The transistors with a channel length of 8 µm operate at 5 V and have a saturation mobility of 2.5 cm2/V·s and an on/off ratio of 5.9×106. Gate-induced surface relief has been found to have strong effect on the performance of the active layer. INTRODUCTION Amorphous metal-oxide semiconductors have attracted a significant amount of attention in the past few years because of their high mobility, transparency due to their wide band gap, stability in ambient air and compatibility with solution-based processing methods. Low fabrication cost and high throughput can be achieved by solution-based processes, such as spin coating, drop casting and various kinds of printing techniques [1,2]. Much effort has been devoted to realizing high-performance solution-processed thin-film transistors (TFTs) with SiO2 as the gate dielectric [2-5], but relatively little attention has been focused on operating these TFTs at low voltage [6,7] and on fabricating devices with small channel length [4] and with a patterned-gate device structure, which are necessary for real circuit applications. In this study, we combined solution-processed zinc tin oxide (ZTO), together with a solution-processed high-k dielectric, ZrO2, to demonstrate a device with low operating voltage and small channel dimensions. A self-aligned process was adopted to minimize parasitic capacitance. Devices with source and drain (S/D) electrodes patterned by photolithography and shadow masking are compared to study the effect of scaling on device performance. Devices with recessed and nonrecessed gate configuration are compared to study the influence of the underlying surface relief on the performance of the spin-coated thin films. EXPERIMENT Both bottom-gate and top-contact structures are employed in this study. The substrate and gate electrode are glass and AuPd, respectively. Different patterning methods of the S/D electrode and different gate electrode configurations are studied. Sample 1 has an un-patterned gate with shadow mask-defined S/D electrodes (figure 1(a)). Sample 2 has an un-patterned gate with photolithographically defined S/D electrodes (figure 1(a)). Sample 3 has a patterned and non-recessed gate with self-aligned S/D electrodes (figure 1(b)). Sample 4 has a patterned and recessed gate with self-aligned S/D electrodes (figure 1(c)).
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