Statistical Modeling of Grain-Enhanced Polysilicon Thin-Film Transistor in Consideration of Grain Boundary Distribution
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A4.13.1
Statistical Modeling of Grain-Enhanced Polysilicon Thin-Film Transistor in Consideration of Grain Boundary Distribution *C. F. Cheng, M. C. Poon, C. W. Kok, and M. Chan, Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong *Correspondence to Tel: (852) 2358 7059, E-mail: [email protected] ABSTRACT A probabilistic model to predict the statistical distribution of grain boundaries in the thin-film transistor (TFT) with an arbitrary transistor-to-grain size ratio is proposed in this paper. Performance of the TFTs, such as carrier mobility, can be estimated and the corresponding performance variation of the fabricated devices becomes predictable when the statistical distribution of grain boundaries is known. The proposed model is still applicable even when the transistor size becomes comparable to the grain size. Reliability and accuracy of the modeling results have been extensively verified by experimental data. It is believed that the model can provide design and optimization guidelines of device variation for grain-enhanced polysilicon TFT technology.
INTRODUCTION Thin-film transistor (TFT) fabricated on polysilicon layer has been substantiated as a promising technology for advanced device applications, such as multi-layer circuit integration [1] and circuit panel fabrication for active matrix liquid crystal display [2]. In order to improve the average carrier mobility in the device’s channel, various grain enhancement technologies, such as metal-induced lateral crystallization (MILC) [3, 4] and excimer laser annealing (ELA) [5], are employed to enlarge the size of polysilicon grains. However everything comes at a price, scaling down the transistor-to-grain size ratio not only results in high carrier mobility in the channel, it also leads to larger device-to-device variation. Statistical variation of the device’s performance is an important factor to be considered especially when the size of the polysilicon grain becomes comparable to the dimension of the transistor. The total amount of grain boundaries (GBs) existed in the channel is definitely a key factor varying the device’s performance. Some previous researches have been done with an assumption that the transistor size is much larger than the grain size [6], but this assumption is not valid to advanced polysilicon TFT technology with the grain size similar to or even larger than the transistor size. A probabilistic model to predict the statistical distribution of GBs formed in the channel will be presented in this paper. The proposed model can be applicable to any transistor-to-grain size ratio. By considering both the distribution of the GBs and its effect on the carrier mobility, device-to-device variation becomes determinable. It is believed that the model can provide important information of transistor size optimization for advanced polysilicon TFT circuit fabrication.
A4.13.2
Ordinary Grain Boundary Pattern
Manhattan Grid Structure
Figure 1. Restoring of an ordinary
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