The MorphoSys Parallel Reconfigurable System
This paper introduces MorphoSys, a parallel system-on-chip which combines a RISC processor with an array of coarse-grain reconfigurable cells. MorphoSys integrates the flexibility of general-purpose systems and high performance levels typical of applicati
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Department of Electrical and Computer Engineering University of California, Irvine Irvine, CA 92715 USA {glu, hsingh, mlee, nader, kurdahi}@ece.uci.edu 2 Department of Systems and Computer Engineering Federal University of Rio de Janeiro/COPPE P.O. Box 68511 21945-970 Rio de Janeiro, RJ Brazil [email protected]
Abstract. This paper introduces MorphoSys, a parallel system-on-chip which combines a RISC processor with an array of coarse-grain reconfigurable cells. MorphoSys integrates the flexibility of general-purpose systems and high performance levels typical of application-specific systems. Simulation results presented here show significant performance enhancements for different classes of applications, as compared to conventional architectures.
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Introduction
General-purpose computing systems provide a single computational substrate for applications with diverse characteristics. These systems are flexible but, due to their generality, they may not match the computational needs of many applications. On the other hand, systems built around Application-Specific Integrated Circuits (ASICs) exploit intrinsic characteristics of an algorithm that lead to a high performance. However, the direct architecture–algorithm mapping restricts the range of applicability of ASIC-based systems. Reconfigurable computing systems represent a hybrid approach between the design paradigms of general-purpose systems and application-specific systems. They combine a software programmable processor and a reconfigurable hardware component which can be customized for different applications. This combination allows reconfigurable systems to achieve performance levels much higher than that obtained with general-purpose systems, with a wider flexibility than that offered by application-specific systems. This paper introduces the MorphoSys parallel reconfigurable system. MorphoSys (Morphoing System) is primarily targeted to applications with inherent parallelism, high regularity, word-level granularity and computation-intensive nature. Some examples of such applications are video compression, image processing, multimedia and data security. However, MorphoSys is flexible enough to support bit-level and irregular applications. P. Amestoy et al. (Eds.): Euro-Par’99, LNCS 1685, pp. 727–734, 1999. c Springer-Verlag Berlin Heidelberg 1999
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Guangming Lu et al.
The remainder of this paper is organized as follows. Section 2 presents the MorphoSys architecture and emphasizes its unique features. Section 3 discusses the status of the MorphoSys prototype currently under development. Section 4 shows performance figures for important applications mapped to MorphoSys. Finally, Section 5 presents the main conclusions.
2 2.1
The MorphoSys System The Architecture
The basic architecture of a parallel reconfigurable system [1] comprises a software programmable core processor and a reconfigurable hardware component. The core processor executes sequential tasks of the application and controls data transfers between the programmable hardware and data mem
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