Thermomechanical Stresses in Copper Interconnect/Low- k Dielectric Systems
- PDF / 180,508 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 98 Downloads / 228 Views
F6.26.1
Thermomechanical Stresses in Copper Interconnect/Low-k Dielectric Systems Y.-L. Shen and E. S. Ege Department of Mechanical Engineering, University of New Mexico Albuquerque, NM 87131, U.S.A. ABSTRACT Numerical simulations of thermal stresses in copper interconnect and low-k dielectric systems are carried out. The analyses include two- and three-dimensional finite element modeling of the interconnect structure. Various combinations of metal, oxide and polymer-based low-k dielectric schemes are considered in the simulation. The evolution of stresses and deformation pattern in copper, barrier layers, and the dielectrics are critically assessed. INTRODUCTION This study concerns thermal stress modeling and its implications in the reliability features of copper (Cu) and/or low-k dielectric-based systems. Recently two-dimensional (2D) finite element analyses have been reported on idealized Cu interconnect/low-k structures [1,2]. A comprehensive 2D study, taking into account the thin-film constitutive properties and a wide variety of geometrical/material features, has also been undertaken [3]. In this paper we first present baseline results from the 2D modeling, and then extend the analyses to a three-dimensional (3D) case where two levels of Cu lines are connected by a via. Attention is devoted to the thermal stresses generated in the Cu lines and via, in the thin barrier layers surrounding the metal structure and part of the dielectric, and in the interlevel dielectric materials. The significance of such an investigation can be understood through the following considerations. • The propensity of void formation and interface damage in Cu depends strongly on the stress/strain state and its spatial distribution. • In general polymer-based and porous low-k materials are mechanically weak. Stresses carried by these materials and the possible consequences need to be carefully assessed. • With the weak dielectric materials in place, a legitimate concern is that the thin barrier (including etch stop) layers may bear the brunt of internal mechanical actions so the reliability of the barrier layers themselves becomes an issue. APPROACH The 2D model features a series of infinite, parallel, single-level Cu lines embedded within the dielectric on top of the silicon (Si) substrate, Fig. 1(a). The metal lines are perpendicular to the paper. Because of the periodicity and symmetry in the lateral (across-the-line, y) direction, only one half of a unit segment is required in the calculation. The model is based on an embedded scheme that low-k dielectric is used only in areas adjacent to the side walls of the metal line while the rest of the dielectric is still silicon oxide (SiOx). Thin tantalum nitride (TaN) and silicon nitride (SiNx) layers, all taken to be 20 nm thick in the structure, serve as diffusion barriers (liners) and/or etch stop. Unless otherwise stated, the Cu line width w and pitch p are taken to be 0.24 and 0.56 µm, respectively, in the 2D model as well as the 3D model described below. The choice of these dimensio
Data Loading...
