Yield Improvement via minimization of step height non-uniformity in Chemical Mechanical Planarization (CMP)
- PDF / 97,329 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 92 Downloads / 204 Views
W5.2.1
Yield Improvement via minimization of step height non-uniformity in Chemical Mechanical Planarization (CMP) Muthukkumar Kadavasal1, Sutee Eamkajornsiri2, Abhijit Chandra1, 3, Ashraf F. Bastawros3, 1 Iowa State University, Ames, Iowa 1 Mechanical Engineering 2 Industrial and Systems Engineering 3 Aerospace Engineering
Abstract Obtaining local and global planarity is one of the prime criteria in dielectric and metal planarizations. Although Chemical Mechanical Planarization (CMP) helps us achieve this criterion in constant pattern density surfaces, the same is not true for variable pattern density surfaces this results in formation of global step heights across the die. This paper provides a pressure open loop control algorithms for obtaining planarity across a die containing variations in pattern densities. Based on the variation of pattern density and surface heights across the die, the surfaces are separated into zones and the pressure is varied spatially and/or temporally to obtain uniform surface heights, with enhanced step height uniformity. One of the algorithms looks ahead and recalculates/modifies the pressure values by identifying the step heights that could be formed after a specified time step. The final surface predictions have improved uniformity on the upper surface as well as on the step heights across the entire die. The simulation would help us track the polishing process for each time step and guide us with the optimized pressure values that can be applied in order to an uniform final surface evolution. 1. Introduction Achieving local as well as global planarization is one of the prime requirements in micro fabrication methods. Many different methods of dielectric planarization are practiced in order to achieve local and global planarity. Chemical mechanical polishing (CMP) has emerged as the planarization method of choice [1] because of its ability to planarize over longer length scales than traditional planarization techniques and is considered to provide far better local and global planarization [2,3,4]. Besides interlayer dielectric planarization, CMP has also find applications in shallow trench isolation, damascene technologies [5, 6]. Despite the advantages that CMP enjoys, the process still suffers from large global non-uniformities within a die and across a wafer. 2. Background Although CMP can planarize over longer length scales, pattern density variation across a chip leads to large variation in global thickness across the die. CMP therefore removes local steps but generates global steps as illustrated in Figure 1. Due to the initial pattern density difference, the two regions on a chip polish at different rates. At some time T1, local planarity is achieved in the low density area of density PD1. After some time T2, local planarity is also achieved in the high density region of initial density PD2. The initial difference in layout pattern density creates a global step height between these two regions due to the difference in removal rates before the local patterns are planarized.[
Data Loading...
